Searched refs:S5P_CLK_SRC0 (Results 1 - 16 of 16) sorted by relevance

/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mach-s5pc100/include/mach/
H A Dregs-clock.h32 #define S5P_CLK_SRC0 S5P_CLKREG(0x200) macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-s5pc100/include/mach/
H A Dregs-clock.h32 #define S5P_CLK_SRC0 S5P_CLKREG(0x200) macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mach-s5p6440/
H A Dclock.c42 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
125 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 2, .size = 1 },
134 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 1, .size = 1 },
646 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 18, .size = 2 },
656 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 2 },
666 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 22, .size = 2 },
676 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 13, .size = 1 },
686 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 14, .size = 2 },
696 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 2 },
706 .reg_src = { .reg = S5P_CLK_SRC0,
[all...]
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-s5p6440/
H A Dclock.c42 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
125 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 2, .size = 1 },
134 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 1, .size = 1 },
646 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 18, .size = 2 },
656 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 2 },
666 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 22, .size = 2 },
676 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 13, .size = 1 },
686 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 14, .size = 2 },
696 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 2 },
706 .reg_src = { .reg = S5P_CLK_SRC0,
[all...]
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mach-s5p6442/
H A Dclock.c38 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
47 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 },
56 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 },
208 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-s5p6442/
H A Dclock.c38 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
47 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 },
56 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 },
208 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mach-s5p6440/include/mach/
H A Dregs-clock.h27 #define S5P_CLK_SRC0 S5P_CLKREG(0x1C) macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mach-s5p6442/include/mach/
H A Dregs-clock.h30 #define S5P_CLK_SRC0 S5P_CLKREG(0x200) macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-s5p6440/include/mach/
H A Dregs-clock.h27 #define S5P_CLK_SRC0 S5P_CLKREG(0x1C) macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-s5p6442/include/mach/
H A Dregs-clock.h30 #define S5P_CLK_SRC0 S5P_CLKREG(0x200) macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mach-s5pv210/
H A Dclock.c40 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
49 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 },
58 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 },
77 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 1 },
124 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 1 },
143 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 24, .size = 1 },
259 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 12, .size = 1 },
695 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 28, .size = 1 },
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-s5pv210/
H A Dclock.c40 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
49 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 },
58 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 },
77 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 1 },
124 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 1 },
143 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 24, .size = 1 },
259 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 12, .size = 1 },
695 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 28, .size = 1 },
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mach-s5pc100/
H A Dclock.c53 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 1 },
81 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 },
91 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
100 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 },
118 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 12, .size = 1 },
191 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 1 },
237 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 24, .size = 1 },
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-s5pc100/
H A Dclock.c53 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 1 },
81 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 },
91 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
100 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 },
118 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 12, .size = 1 },
191 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 1 },
237 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 24, .size = 1 },
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mach-s5pv210/include/mach/
H A Dregs-clock.h30 #define S5P_CLK_SRC0 S5P_CLKREG(0x200) macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-s5pv210/include/mach/
H A Dregs-clock.h30 #define S5P_CLK_SRC0 S5P_CLKREG(0x200) macro

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