Searched refs:S5P_CLK_DIV3 (Results 1 - 14 of 14) sorted by relevance

/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mach-s5pc100/include/mach/
H A Dregs-clock.h40 #define S5P_CLK_DIV3 S5P_CLKREG(0x30C) macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-s5pc100/include/mach/
H A Dregs-clock.h40 #define S5P_CLK_DIV3 S5P_CLKREG(0x30C) macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mach-s5p6440/include/mach/
H A Dregs-clock.h36 #define S5P_CLK_DIV3 S5P_CLKREG(0x40) macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mach-s5p6442/include/mach/
H A Dregs-clock.h44 #define S5P_CLK_DIV3 S5P_CLKREG(0x30C) macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mach-s5pc100/
H A Dclock.c273 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 28, .size = 4 },
1045 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 12, .size = 4 },
1056 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 16, .size = 4 },
1067 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 20, .size = 4 },
1078 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 24, .size = 4 },
1089 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 0, .size = 4 },
1100 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 4, .size = 4 },
1111 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 8, .size = 4 },
1122 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 8, .size = 4 },
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-s5p6440/include/mach/
H A Dregs-clock.h36 #define S5P_CLK_DIV3 S5P_CLKREG(0x40) macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-s5p6442/include/mach/
H A Dregs-clock.h44 #define S5P_CLK_DIV3 S5P_CLKREG(0x30C) macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-s5pc100/
H A Dclock.c273 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 28, .size = 4 },
1045 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 12, .size = 4 },
1056 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 16, .size = 4 },
1067 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 20, .size = 4 },
1078 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 24, .size = 4 },
1089 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 0, .size = 4 },
1100 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 4, .size = 4 },
1111 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 8, .size = 4 },
1122 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 8, .size = 4 },
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mach-s5p6440/
H A Dclock.c286 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 8, .size = 4 },
295 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 12, .size = 4 },
717 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 0, .size = 4 },
727 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 4, .size = 4 },
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mach-s5pv210/include/mach/
H A Dregs-clock.h44 #define S5P_CLK_DIV3 S5P_CLKREG(0x30C) macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-s5p6440/
H A Dclock.c286 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 8, .size = 4 },
295 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 12, .size = 4 },
717 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 0, .size = 4 },
727 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 4, .size = 4 },
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-s5pv210/include/mach/
H A Dregs-clock.h44 #define S5P_CLK_DIV3 S5P_CLKREG(0x30C) macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mach-s5pv210/
H A Dclock.c764 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 12, .size = 4 },
774 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 16, .size = 4 },
784 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 20, .size = 4 },
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-s5pv210/
H A Dclock.c764 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 12, .size = 4 },
774 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 16, .size = 4 },
784 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 20, .size = 4 },

Completed in 121 milliseconds