Searched refs:S5P_CLK_DIV1 (Results 1 - 14 of 14) sorted by relevance

/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mach-s5pc100/include/mach/
H A Dregs-clock.h38 #define S5P_CLK_DIV1 S5P_CLKREG(0x304) macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-s5pc100/include/mach/
H A Dregs-clock.h38 #define S5P_CLK_DIV1 S5P_CLKREG(0x304) macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mach-s5p6440/include/mach/
H A Dregs-clock.h29 #define S5P_CLK_DIV1 S5P_CLKREG(0x24) macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mach-s5p6442/include/mach/
H A Dregs-clock.h42 #define S5P_CLK_DIV1 S5P_CLKREG(0x304) macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-s5p6440/include/mach/
H A Dregs-clock.h29 #define S5P_CLK_DIV1 S5P_CLKREG(0x24) macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-s5p6442/include/mach/
H A Dregs-clock.h42 #define S5P_CLK_DIV1 S5P_CLKREG(0x304) macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mach-s5pc100/
H A Dclock.c172 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 3 },
200 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 12, .size = 3 },
209 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 8, .size = 1 },
218 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 4, .size = 2 },
246 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 20, .size = 2 },
255 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 16, .size = 3 },
264 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 24, .size = 5 },
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-s5pc100/
H A Dclock.c172 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 3 },
200 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 12, .size = 3 },
209 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 8, .size = 1 },
218 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 4, .size = 2 },
246 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 20, .size = 2 },
255 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 16, .size = 3 },
264 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 24, .size = 5 },
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mach-s5p6440/
H A Dclock.c647 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 4 },
657 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 4, .size = 4 },
667 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 8, .size = 4 },
707 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 12, .size = 4 },
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mach-s5pv210/include/mach/
H A Dregs-clock.h42 #define S5P_CLK_DIV1 S5P_CLKREG(0x304) macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-s5p6440/
H A Dclock.c647 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 4 },
657 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 4, .size = 4 },
667 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 8, .size = 4 },
707 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 12, .size = 4 },
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-s5pv210/include/mach/
H A Dregs-clock.h42 #define S5P_CLK_DIV1 S5P_CLKREG(0x304) macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mach-s5pv210/
H A Dclock.c531 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 4},
794 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 12, .size = 4 },
804 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 16, .size = 4 },
814 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 20, .size = 4 },
894 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 28, .size = 4 },
980 clkdiv1 = __raw_readl(S5P_CLK_DIV1);
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-s5pv210/
H A Dclock.c531 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 4},
794 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 12, .size = 4 },
804 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 16, .size = 4 },
814 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 20, .size = 4 },
894 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 28, .size = 4 },
980 clkdiv1 = __raw_readl(S5P_CLK_DIV1);

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