Searched refs:S5P_CLKDIV_PERIL0 (Results 1 - 4 of 4) sorted by relevance

/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mach-s5pv310/include/mach/
H A Dregs-clock.h34 #define S5P_CLKDIV_PERIL0 S5P_CLKREG(0x0C550) macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-s5pv310/include/mach/
H A Dregs-clock.h34 #define S5P_CLKDIV_PERIL0 S5P_CLKREG(0x0C550) macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mach-s5pv310/
H A Dclock.c410 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 0, .size = 4 },
420 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 4, .size = 4 },
430 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 8, .size = 4 },
440 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 12, .size = 4 },
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-s5pv310/
H A Dclock.c410 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 0, .size = 4 },
420 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 4, .size = 4 },
430 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 8, .size = 4 },
440 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 12, .size = 4 },

Completed in 53 milliseconds