Searched refs:S3C_CLK_DIV0 (Results 1 - 6 of 6) sorted by relevance

/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mach-s3c64xx/
H A Dclock.c399 clkdiv = __raw_readl(S3C_CLK_DIV0) & armclk_mask;
432 val = __raw_readl(S3C_CLK_DIV0);
435 __raw_writel(val, S3C_CLK_DIV0);
458 if (__raw_readl(S3C_CLK_DIV0) & S3C6400_CLKDIV0_MPLL_MASK)
722 .reg_div = { .reg = S3C_CLK_DIV0, .shift = 20, .size = 4 },
754 clkdiv0 = __raw_readl(S3C_CLK_DIV0);
H A Dpm.c62 SAVE_ITEM(S3C_CLK_DIV0),
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-s3c64xx/
H A Dclock.c399 clkdiv = __raw_readl(S3C_CLK_DIV0) & armclk_mask;
432 val = __raw_readl(S3C_CLK_DIV0);
435 __raw_writel(val, S3C_CLK_DIV0);
458 if (__raw_readl(S3C_CLK_DIV0) & S3C6400_CLKDIV0_MPLL_MASK)
722 .reg_div = { .reg = S3C_CLK_DIV0, .shift = 20, .size = 4 },
754 clkdiv0 = __raw_readl(S3C_CLK_DIV0);
H A Dpm.c62 SAVE_ITEM(S3C_CLK_DIV0),
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mach-s3c64xx/include/mach/
H A Dregs-clock.h28 #define S3C_CLK_DIV0 S3C_CLKREG(0x20) macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-s3c64xx/include/mach/
H A Dregs-clock.h28 #define S3C_CLK_DIV0 S3C_CLKREG(0x20) macro

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