/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/staging/rtl8192su/ |
H A D | r8192S_rtl8225.c | 70 rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A, RF_CHNLBW, BIT10|BIT11, 0x01); 76 rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A, RF_CHNLBW, BIT10|BIT11, 0x00); 91 //rtl8192_phy_SetRFReg(Adapter, (RF90_RADIO_PATH_E)RF90_PATH_A, RF_CHNLBW, (BIT10|BIT11), 0x01); 94 //rtl8192_phy_SetRFReg(Adapter, (RF90_RADIO_PATH_E)RF90_PATH_A, RF_CHNLBW, (BIT10|BIT11), 0x00); 128 //for(eRFPath = RF90_PATH_A; eRFPath <pHalData->NumTotalRFPath; eRFPath++) 216 //for(eRFPath = RF90_PATH_A; eRFPath <pHalData->NumTotalRFPath; eRFPath++) 225 case RF90_PATH_A: 249 case RF90_PATH_A: 266 case RF90_PATH_A:
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H A D | r8192S_rtl6052.c | 121 rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A, RF_CHNLBW, BIT10|BIT11, 0x01); 127 rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A, RF_CHNLBW, BIT10|BIT11, 0x00); 225 Legacy_pwrdiff = priv->TxPwrLegacyHtDiff[RF90_PATH_A][Channel-1]; 238 BandEdge_Pwrdiff = priv->TxPwrbandEdgeLegacyOfdm[RF90_PATH_A][0]; 241 BandEdge_Pwrdiff = priv->TxPwrbandEdgeLegacyOfdm[RF90_PATH_A][1]; 263 HT20_pwrdiff = priv->TxPwrHt20Diff[RF90_PATH_A][Channel-1]; 282 BandEdge_Pwrdiff = priv->TxPwrbandEdgeHt40[RF90_PATH_A][0]; 284 BandEdge_Pwrdiff = priv->TxPwrbandEdgeHt40[RF90_PATH_A][1]; 294 BandEdge_Pwrdiff = priv->TxPwrbandEdgeHt20[RF90_PATH_A][0]; 296 BandEdge_Pwrdiff = priv->TxPwrbandEdgeHt20[RF90_PATH_A][ [all...] |
H A D | r8192S_phy.c | 1008 case RF90_PATH_A: 1201 for(eRFPath=(RF90_RADIO_PATH_E)RF90_PATH_A; eRFPath < RF90_PATH_MAX; eRFPath++) 1314 priv->PHYRegDef[RF90_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; // 16 LSBs if read 32-bit from 0x870 1320 priv->PHYRegDef[RF90_PATH_A].rfintfi = rFPGA0_XAB_RFInterfaceRB; // 16 LSBs if read 32-bit from 0x8E0 1326 priv->PHYRegDef[RF90_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE; // 16 LSBs if read 32-bit from 0x860 1332 priv->PHYRegDef[RF90_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE; // 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862) 1338 priv->PHYRegDef[RF90_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter; //LSSI Parameter 1344 priv->PHYRegDef[RF90_PATH_A].rfLSSI_Select = rFPGA0_XAB_RFParameter; //BB Band Select 1350 priv->PHYRegDef[RF90_PATH_A].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage 1356 priv->PHYRegDef[RF90_PATH_A] [all...] |
H A D | r8192S_phy.h | 77 RF90_PATH_A = 0, //Radio Path A enumerator in enum:_RF90_RADIO_PATH
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H A D | r8192U_core.c | 3890 priv->TxPwrHt20Diff[RF90_PATH_A][i] = (tempval&0xF); 3902 priv->TxPwrLegacyHtDiff[RF90_PATH_A][i] = (tempval&0xF); 3910 priv->TxPwrbandEdgeHt40[RF90_PATH_A][0] = (tempval&0xF); // Band edge low channel 3911 priv->TxPwrbandEdgeHt40[RF90_PATH_A][1] = ((tempval>>4)&0xF); // Band edge high channel 3917 priv->TxPwrbandEdgeHt20[RF90_PATH_A][0] = (tempval&0xF); // Band edge low channel 3918 priv->TxPwrbandEdgeHt20[RF90_PATH_A][1] = ((tempval>>4)&0xF); // Band edge high channel 3924 priv->TxPwrbandEdgeLegacyOfdm[RF90_PATH_A][0] = (tempval&0xF); // Band edge low channel 3925 priv->TxPwrbandEdgeLegacyOfdm[RF90_PATH_A][1] = ((tempval>>4)&0xF); // Band edge high channel 3934 RT_TRACE(COMP_INIT, "RF-A Ht20 to HT40 Diff[%d] = 0x%x\n", i, priv->TxPwrHt20Diff[RF90_PATH_A][i]); 3936 RT_TRACE(COMP_INIT, "RF-A Legacy to Ht40 Diff[%d] = 0x%x\n", i, priv->TxPwrLegacyHtDiff[RF90_PATH_A][ [all...] |
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/staging/rtl8192su/ |
H A D | r8192S_rtl8225.c | 70 rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A, RF_CHNLBW, BIT10|BIT11, 0x01); 76 rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A, RF_CHNLBW, BIT10|BIT11, 0x00); 91 //rtl8192_phy_SetRFReg(Adapter, (RF90_RADIO_PATH_E)RF90_PATH_A, RF_CHNLBW, (BIT10|BIT11), 0x01); 94 //rtl8192_phy_SetRFReg(Adapter, (RF90_RADIO_PATH_E)RF90_PATH_A, RF_CHNLBW, (BIT10|BIT11), 0x00); 128 //for(eRFPath = RF90_PATH_A; eRFPath <pHalData->NumTotalRFPath; eRFPath++) 216 //for(eRFPath = RF90_PATH_A; eRFPath <pHalData->NumTotalRFPath; eRFPath++) 225 case RF90_PATH_A: 249 case RF90_PATH_A: 266 case RF90_PATH_A:
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H A D | r8192S_rtl6052.c | 121 rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A, RF_CHNLBW, BIT10|BIT11, 0x01); 127 rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A, RF_CHNLBW, BIT10|BIT11, 0x00); 225 Legacy_pwrdiff = priv->TxPwrLegacyHtDiff[RF90_PATH_A][Channel-1]; 238 BandEdge_Pwrdiff = priv->TxPwrbandEdgeLegacyOfdm[RF90_PATH_A][0]; 241 BandEdge_Pwrdiff = priv->TxPwrbandEdgeLegacyOfdm[RF90_PATH_A][1]; 263 HT20_pwrdiff = priv->TxPwrHt20Diff[RF90_PATH_A][Channel-1]; 282 BandEdge_Pwrdiff = priv->TxPwrbandEdgeHt40[RF90_PATH_A][0]; 284 BandEdge_Pwrdiff = priv->TxPwrbandEdgeHt40[RF90_PATH_A][1]; 294 BandEdge_Pwrdiff = priv->TxPwrbandEdgeHt20[RF90_PATH_A][0]; 296 BandEdge_Pwrdiff = priv->TxPwrbandEdgeHt20[RF90_PATH_A][ [all...] |
H A D | r8192S_phy.c | 1008 case RF90_PATH_A: 1201 for(eRFPath=(RF90_RADIO_PATH_E)RF90_PATH_A; eRFPath < RF90_PATH_MAX; eRFPath++) 1314 priv->PHYRegDef[RF90_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; // 16 LSBs if read 32-bit from 0x870 1320 priv->PHYRegDef[RF90_PATH_A].rfintfi = rFPGA0_XAB_RFInterfaceRB; // 16 LSBs if read 32-bit from 0x8E0 1326 priv->PHYRegDef[RF90_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE; // 16 LSBs if read 32-bit from 0x860 1332 priv->PHYRegDef[RF90_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE; // 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862) 1338 priv->PHYRegDef[RF90_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter; //LSSI Parameter 1344 priv->PHYRegDef[RF90_PATH_A].rfLSSI_Select = rFPGA0_XAB_RFParameter; //BB Band Select 1350 priv->PHYRegDef[RF90_PATH_A].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage 1356 priv->PHYRegDef[RF90_PATH_A] [all...] |
H A D | r8192S_phy.h | 77 RF90_PATH_A = 0, //Radio Path A enumerator in enum:_RF90_RADIO_PATH
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H A D | r8192U_core.c | 3890 priv->TxPwrHt20Diff[RF90_PATH_A][i] = (tempval&0xF); 3902 priv->TxPwrLegacyHtDiff[RF90_PATH_A][i] = (tempval&0xF); 3910 priv->TxPwrbandEdgeHt40[RF90_PATH_A][0] = (tempval&0xF); // Band edge low channel 3911 priv->TxPwrbandEdgeHt40[RF90_PATH_A][1] = ((tempval>>4)&0xF); // Band edge high channel 3917 priv->TxPwrbandEdgeHt20[RF90_PATH_A][0] = (tempval&0xF); // Band edge low channel 3918 priv->TxPwrbandEdgeHt20[RF90_PATH_A][1] = ((tempval>>4)&0xF); // Band edge high channel 3924 priv->TxPwrbandEdgeLegacyOfdm[RF90_PATH_A][0] = (tempval&0xF); // Band edge low channel 3925 priv->TxPwrbandEdgeLegacyOfdm[RF90_PATH_A][1] = ((tempval>>4)&0xF); // Band edge high channel 3934 RT_TRACE(COMP_INIT, "RF-A Ht20 to HT40 Diff[%d] = 0x%x\n", i, priv->TxPwrHt20Diff[RF90_PATH_A][i]); 3936 RT_TRACE(COMP_INIT, "RF-A Legacy to Ht40 Diff[%d] = 0x%x\n", i, priv->TxPwrLegacyHtDiff[RF90_PATH_A][ [all...] |
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/staging/rtl8192u/ |
H A D | r8190_rtl8256.c | 31 //for(eRFPath = RF90_PATH_A; eRFPath <pHalData->NumTotalRFPath; eRFPath++) 125 for(eRFPath = (RF90_RADIO_PATH_E)RF90_PATH_A; eRFPath <priv->NumTotalRFPath; eRFPath++) 138 case RF90_PATH_A: 173 case RF90_PATH_A: 214 case RF90_PATH_A:
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H A D | r819xU_phy.c | 71 if (eRFPath == RF90_PATH_A || eRFPath == RF90_PATH_B) 584 priv->PHYRegDef[RF90_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; // 16 LSBs if read 32-bit from 0x870 590 priv->PHYRegDef[RF90_PATH_A].rfintfi = rFPGA0_XAB_RFInterfaceRB; // 16 LSBs if read 32-bit from 0x8E0 596 priv->PHYRegDef[RF90_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE; // 16 LSBs if read 32-bit from 0x860 602 priv->PHYRegDef[RF90_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE; // 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862) 608 priv->PHYRegDef[RF90_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter; //LSSI Parameter 614 priv->PHYRegDef[RF90_PATH_A].rfLSSI_Select = rFPGA0_XAB_RFParameter; //BB Band Select 620 priv->PHYRegDef[RF90_PATH_A].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage 626 priv->PHYRegDef[RF90_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1; //wire control parameter1 632 priv->PHYRegDef[RF90_PATH_A] [all...] |
H A D | r819xU_phy.h | 45 RF90_PATH_A = 0, //Radio Path A enumerator in enum:_RF90_RADIO_PATH
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/staging/rtl8192u/ |
H A D | r8190_rtl8256.c | 31 //for(eRFPath = RF90_PATH_A; eRFPath <pHalData->NumTotalRFPath; eRFPath++) 125 for(eRFPath = (RF90_RADIO_PATH_E)RF90_PATH_A; eRFPath <priv->NumTotalRFPath; eRFPath++) 138 case RF90_PATH_A: 173 case RF90_PATH_A: 214 case RF90_PATH_A:
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H A D | r819xU_phy.c | 71 if (eRFPath == RF90_PATH_A || eRFPath == RF90_PATH_B) 584 priv->PHYRegDef[RF90_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; // 16 LSBs if read 32-bit from 0x870 590 priv->PHYRegDef[RF90_PATH_A].rfintfi = rFPGA0_XAB_RFInterfaceRB; // 16 LSBs if read 32-bit from 0x8E0 596 priv->PHYRegDef[RF90_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE; // 16 LSBs if read 32-bit from 0x860 602 priv->PHYRegDef[RF90_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE; // 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862) 608 priv->PHYRegDef[RF90_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter; //LSSI Parameter 614 priv->PHYRegDef[RF90_PATH_A].rfLSSI_Select = rFPGA0_XAB_RFParameter; //BB Band Select 620 priv->PHYRegDef[RF90_PATH_A].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage 626 priv->PHYRegDef[RF90_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1; //wire control parameter1 632 priv->PHYRegDef[RF90_PATH_A] [all...] |
H A D | r819xU_phy.h | 45 RF90_PATH_A = 0, //Radio Path A enumerator in enum:_RF90_RADIO_PATH
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/staging/rtl8192e/ |
H A D | r819xE_phy.h | 88 RF90_PATH_A = 0, enumerator in enum:_RF90_RADIO_PATH
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H A D | r819xE_phy.c | 1437 if(eRFPath == RF90_PATH_A || eRFPath == RF90_PATH_B) 1448 if (eRFPath == RF90_PATH_A || eRFPath == RF90_PATH_B) 2058 priv->PHYRegDef[RF90_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; // 16 LSBs if read 32-bit from 0x870 2064 priv->PHYRegDef[RF90_PATH_A].rfintfi = rFPGA0_XAB_RFInterfaceRB; // 16 LSBs if read 32-bit from 0x8E0 2070 priv->PHYRegDef[RF90_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE; // 16 LSBs if read 32-bit from 0x860 2076 priv->PHYRegDef[RF90_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE; // 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862) 2082 priv->PHYRegDef[RF90_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter; //LSSI Parameter 2088 priv->PHYRegDef[RF90_PATH_A].rfLSSI_Select = rFPGA0_XAB_RFParameter; //BB Band Select 2094 priv->PHYRegDef[RF90_PATH_A].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage 2100 priv->PHYRegDef[RF90_PATH_A] [all...] |
H A D | r8190_rtl8256.c | 31 //for(eRFPath = RF90_PATH_A; eRFPath <pHalData->NumTotalRFPath; eRFPath++) 119 for(eRFPath = (RF90_RADIO_PATH_E)RF90_PATH_A; eRFPath <priv->NumTotalRFPath; eRFPath++) 132 case RF90_PATH_A: 168 case RF90_PATH_A: 209 case RF90_PATH_A:
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H A D | r8192E_core.c | 5104 for(i=RF90_PATH_A; i<RF90_PATH_MAX; i++) 5110 for(i=RF90_PATH_A; i<RF90_PATH_MAX; i++) 5119 for(i=RF90_PATH_A; i<RF90_PATH_MAX; i++) 5124 for(i=RF90_PATH_A; i<RF90_PATH_MAX; i++) 5225 for (rfpath = RF90_PATH_A; rfpath < RF90_PATH_C; rfpath++) 5549 for(i=RF90_PATH_A; i<RF90_PATH_MAX; i++) 5640 for(i=RF90_PATH_A; i<RF90_PATH_MAX; i++)
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H A D | r8192E_dm.c | 957 tmpRegA = rtl8192_phy_QueryRFReg(dev, RF90_PATH_A, 0x12, 0x078); // 0x12: RF Reg[10:7] 1633 rtl8192_phy_SetRFReg(dev, RF90_PATH_A, 0x02, bMask12Bits, 0x4d); 1634 rtl8192_phy_SetRFReg(dev, RF90_PATH_A, 0x02, bMask12Bits, 0x4f); 1635 rtl8192_phy_SetRFReg(dev, RF90_PATH_A, 0x02, bMask12Bits, 0x4d); 1636 rtl8192_phy_SetRFReg(dev, RF90_PATH_A, 0x02, bMask12Bits, 0x4f);
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/staging/rtl8192e/ |
H A D | r819xE_phy.h | 88 RF90_PATH_A = 0, enumerator in enum:_RF90_RADIO_PATH
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H A D | r819xE_phy.c | 1437 if(eRFPath == RF90_PATH_A || eRFPath == RF90_PATH_B) 1448 if (eRFPath == RF90_PATH_A || eRFPath == RF90_PATH_B) 2058 priv->PHYRegDef[RF90_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; // 16 LSBs if read 32-bit from 0x870 2064 priv->PHYRegDef[RF90_PATH_A].rfintfi = rFPGA0_XAB_RFInterfaceRB; // 16 LSBs if read 32-bit from 0x8E0 2070 priv->PHYRegDef[RF90_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE; // 16 LSBs if read 32-bit from 0x860 2076 priv->PHYRegDef[RF90_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE; // 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862) 2082 priv->PHYRegDef[RF90_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter; //LSSI Parameter 2088 priv->PHYRegDef[RF90_PATH_A].rfLSSI_Select = rFPGA0_XAB_RFParameter; //BB Band Select 2094 priv->PHYRegDef[RF90_PATH_A].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage 2100 priv->PHYRegDef[RF90_PATH_A] [all...] |
H A D | r8190_rtl8256.c | 31 //for(eRFPath = RF90_PATH_A; eRFPath <pHalData->NumTotalRFPath; eRFPath++) 119 for(eRFPath = (RF90_RADIO_PATH_E)RF90_PATH_A; eRFPath <priv->NumTotalRFPath; eRFPath++) 132 case RF90_PATH_A: 168 case RF90_PATH_A: 209 case RF90_PATH_A:
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H A D | r8192E_core.c | 5104 for(i=RF90_PATH_A; i<RF90_PATH_MAX; i++) 5110 for(i=RF90_PATH_A; i<RF90_PATH_MAX; i++) 5119 for(i=RF90_PATH_A; i<RF90_PATH_MAX; i++) 5124 for(i=RF90_PATH_A; i<RF90_PATH_MAX; i++) 5225 for (rfpath = RF90_PATH_A; rfpath < RF90_PATH_C; rfpath++) 5549 for(i=RF90_PATH_A; i<RF90_PATH_MAX; i++) 5640 for(i=RF90_PATH_A; i<RF90_PATH_MAX; i++)
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