/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/atm/ |
H A D | midway.h | 22 #define REG_BASE 0x00040000 /* offset of Midway register area */ macro
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H A D | iphase.h | 633 #define REG_BASE IPHASE5575_BUS_CONTROL_REG_BASE macro
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H A D | eni.c | 1706 eni_dev->reg = base+REG_BASE;
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H A D | iphase.c | 2221 iadev->reg = base + REG_BASE;
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/atm/ |
H A D | midway.h | 22 #define REG_BASE 0x00040000 /* offset of Midway register area */ macro
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H A D | iphase.h | 633 #define REG_BASE IPHASE5575_BUS_CONTROL_REG_BASE macro
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H A D | eni.c | 1706 eni_dev->reg = base+REG_BASE;
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H A D | iphase.c | 2221 iadev->reg = base + REG_BASE;
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt/router/gdb/opcodes/ |
H A D | tic80-opc.c | 475 #define REG_BASE (CR_LI + 1) 481 #define REG_BASE_M_SI (REG_BASE + 1) 939 {"jsr", OP_SI(0x44), MASK_SI, 0, {OFF_SS_BR, REG_BASE, REG_DEST} }, 940 {"jsr", OP_LI(0x389), MASK_LI, 0, {OFF_SL_BR, REG_BASE, REG_DEST} }, 941 {"jsr", OP_REG(0x388), MASK_REG, 0, {REG_0, REG_BASE, REG_DEST} }, 942 {"jsr.a", OP_SI(0x45), MASK_SI, 0, {OFF_SS_BR, REG_BASE, REG_DEST} }, 943 {"jsr.a", OP_LI(0x38B), MASK_LI, 0, {OFF_SL_BR, REG_BASE, REG_DEST} }, 944 {"jsr.a", OP_REG(0x38A), MASK_REG, 0, {REG_0, REG_BASE, REG_DEST} }, 473 #define REG_BASE macro
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src/router/gdb/opcodes/ |
H A D | tic80-opc.c | 475 #define REG_BASE (CR_LI + 1) 481 #define REG_BASE_M_SI (REG_BASE + 1) 939 {"jsr", OP_SI(0x44), MASK_SI, 0, {OFF_SS_BR, REG_BASE, REG_DEST} }, 940 {"jsr", OP_LI(0x389), MASK_LI, 0, {OFF_SL_BR, REG_BASE, REG_DEST} }, 941 {"jsr", OP_REG(0x388), MASK_REG, 0, {REG_0, REG_BASE, REG_DEST} }, 942 {"jsr.a", OP_SI(0x45), MASK_SI, 0, {OFF_SS_BR, REG_BASE, REG_DEST} }, 943 {"jsr.a", OP_LI(0x38B), MASK_LI, 0, {OFF_SL_BR, REG_BASE, REG_DEST} }, 944 {"jsr.a", OP_REG(0x38A), MASK_REG, 0, {REG_0, REG_BASE, REG_DEST} }, 473 #define REG_BASE macro
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/router/gdb/opcodes/ |
H A D | tic80-opc.c | 475 #define REG_BASE (CR_LI + 1) 481 #define REG_BASE_M_SI (REG_BASE + 1) 939 {"jsr", OP_SI(0x44), MASK_SI, 0, {OFF_SS_BR, REG_BASE, REG_DEST} }, 940 {"jsr", OP_LI(0x389), MASK_LI, 0, {OFF_SL_BR, REG_BASE, REG_DEST} }, 941 {"jsr", OP_REG(0x388), MASK_REG, 0, {REG_0, REG_BASE, REG_DEST} }, 942 {"jsr.a", OP_SI(0x45), MASK_SI, 0, {OFF_SS_BR, REG_BASE, REG_DEST} }, 943 {"jsr.a", OP_LI(0x38B), MASK_LI, 0, {OFF_SL_BR, REG_BASE, REG_DEST} }, 944 {"jsr.a", OP_REG(0x38A), MASK_REG, 0, {REG_0, REG_BASE, REG_DEST} }, 473 #define REG_BASE macro
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