Searched refs:REGBASE (Results 1 - 14 of 14) sorted by relevance

/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/mips/include/asm/emma/
H A Demma2rh.h29 #define REGBASE 0x10000000 macro
31 #define EMMA2RH_BHIF_STRAP_0 (0x000010+REGBASE)
32 #define EMMA2RH_BHIF_INT_ST_0 (0x000030+REGBASE)
33 #define EMMA2RH_BHIF_INT_ST_1 (0x000034+REGBASE)
34 #define EMMA2RH_BHIF_INT_ST_2 (0x000038+REGBASE)
35 #define EMMA2RH_BHIF_INT_EN_0 (0x000040+REGBASE)
36 #define EMMA2RH_BHIF_INT_EN_1 (0x000044+REGBASE)
37 #define EMMA2RH_BHIF_INT_EN_2 (0x000048+REGBASE)
38 #define EMMA2RH_BHIF_INT1_EN_0 (0x000050+REGBASE)
39 #define EMMA2RH_BHIF_INT1_EN_1 (0x000054+REGBASE)
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/mips/include/asm/emma/
H A Demma2rh.h29 #define REGBASE 0x10000000 macro
31 #define EMMA2RH_BHIF_STRAP_0 (0x000010+REGBASE)
32 #define EMMA2RH_BHIF_INT_ST_0 (0x000030+REGBASE)
33 #define EMMA2RH_BHIF_INT_ST_1 (0x000034+REGBASE)
34 #define EMMA2RH_BHIF_INT_ST_2 (0x000038+REGBASE)
35 #define EMMA2RH_BHIF_INT_EN_0 (0x000040+REGBASE)
36 #define EMMA2RH_BHIF_INT_EN_1 (0x000044+REGBASE)
37 #define EMMA2RH_BHIF_INT_EN_2 (0x000048+REGBASE)
38 #define EMMA2RH_BHIF_INT1_EN_0 (0x000050+REGBASE)
39 #define EMMA2RH_BHIF_INT1_EN_1 (0x000054+REGBASE)
[all...]
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/mips/include/asm/mach-rc32434/
H A Dirq.h10 #define IC_GROUP0_PEND (REGBASE + 0x38000)
11 #define IC_GROUP0_MASK (REGBASE + 0x38008)
H A Drb.h20 #define REGBASE 0x18000000 macro
21 #define IDT434_REG_BASE ((volatile void *) KSEG1ADDR(REGBASE))
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/mips/include/asm/mach-rc32434/
H A Dirq.h10 #define IC_GROUP0_PEND (REGBASE + 0x38000)
11 #define IC_GROUP0_MASK (REGBASE + 0x38008)
H A Drb.h20 #define REGBASE 0x18000000 macro
21 #define IDT434_REG_BASE ((volatile void *) KSEG1ADDR(REGBASE))
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/mips/rb532/
H A Dserial.c43 .membase = (char *)KSEG1ADDR(REGBASE + UART0BASE),
H A Dgpio.c47 .start = REGBASE + GPIOBASE,
48 .end = REGBASE + GPIOBASE + sizeof(struct rb532_gpio_reg) - 1,
H A Ddevices.c225 .membase = (char *)KSEG1ADDR(REGBASE + UART0BASE),
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/mips/rb532/
H A Dserial.c43 .membase = (char *)KSEG1ADDR(REGBASE + UART0BASE),
H A Dgpio.c47 .start = REGBASE + GPIOBASE,
48 .end = REGBASE + GPIOBASE + sizeof(struct rb532_gpio_reg) - 1,
H A Ddevices.c225 .membase = (char *)KSEG1ADDR(REGBASE + UART0BASE),
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/net/wan/
H A Dwanxlfw.S89 REGBASE = DPRBASE + 0x1000 define
90 PICR = REGBASE + 0x026 // 16-bit periodic irq control
91 PITR = REGBASE + 0x02A // 16-bit periodic irq timing
92 OR1 = REGBASE + 0x064 // 32-bit RAM bank #1 options
93 CICR = REGBASE + 0x540 // 32(24)-bit CP interrupt config
94 CIMR = REGBASE + 0x548 // 32-bit CP interrupt mask
95 CISR = REGBASE + 0x54C // 32-bit CP interrupts in-service
96 PADIR = REGBASE + 0x550 // 16-bit PortA data direction bitmap
97 PAPAR = REGBASE + 0x552 // 16-bit PortA pin assignment bitmap
98 PAODR = REGBASE
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/net/wan/
H A Dwanxlfw.S89 REGBASE = DPRBASE + 0x1000 define
90 PICR = REGBASE + 0x026 // 16-bit periodic irq control
91 PITR = REGBASE + 0x02A // 16-bit periodic irq timing
92 OR1 = REGBASE + 0x064 // 32-bit RAM bank #1 options
93 CICR = REGBASE + 0x540 // 32(24)-bit CP interrupt config
94 CIMR = REGBASE + 0x548 // 32-bit CP interrupt mask
95 CISR = REGBASE + 0x54C // 32-bit CP interrupts in-service
96 PADIR = REGBASE + 0x550 // 16-bit PortA data direction bitmap
97 PAPAR = REGBASE + 0x552 // 16-bit PortA pin assignment bitmap
98 PAODR = REGBASE
[all...]

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