Searched refs:RCSR (Results 1 - 18 of 18) sorted by relevance
| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mach-sa1100/include/mach/ |
| H A D | reset.h | 15 RCSR = mask;
|
| H A D | SA-1100.h | 1040 * RCSR Reset Controller (RC) Status Register (read/write).
1044 #define RCSR __REG(0x90030004) /* RC Status Reg. */ macro
|
| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-sa1100/include/mach/ |
| H A D | reset.h | 15 RCSR = mask;
|
| H A D | SA-1100.h | 1040 * RCSR Reset Controller (RC) Status Register (read/write).
1044 #define RCSR __REG(0x90030004) /* RC Status Reg. */ macro
|
| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mach-pxa/ |
| H A D | pxa2xx.c | 25 /* RESET_STATUS_* has a 1:1 mapping with RCSR */
26 RCSR = mask;
|
| H A D | pxa25x.c | 242 RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR;
351 reset_status = RCSR;
|
| H A D | pxa27x.c | 286 RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR;
413 reset_status = RCSR;
|
| H A D | sharpsl_pm.c | 595 RCSR = 0x0f;
|
| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-pxa/ |
| H A D | pxa2xx.c | 25 /* RESET_STATUS_* has a 1:1 mapping with RCSR */
26 RCSR = mask;
|
| H A D | pxa25x.c | 242 RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR;
351 reset_status = RCSR;
|
| H A D | pxa27x.c | 286 RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR;
413 reset_status = RCSR;
|
| H A D | sharpsl_pm.c | 595 RCSR = 0x0f;
|
| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mach-sa1100/ |
| H A D | pm.c | 73 RCSR = RCSR_HWR | RCSR_SWR | RCSR_WDR | RCSR_SMR;
|
| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-sa1100/ |
| H A D | pm.c | 73 RCSR = RCSR_HWR | RCSR_SWR | RCSR_WDR | RCSR_SMR;
|
| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mach-pxa/include/mach/ |
| H A D | pxa2xx-regs.h | 101 #define RCSR __REG(0x40F00030) /* Reset Controller Status Register */ macro
|
| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-pxa/include/mach/ |
| H A D | pxa2xx-regs.h | 101 #define RCSR __REG(0x40F00030) /* Reset Controller Status Register */ macro
|
| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/char/ |
| H A D | synclink.c | 362 #define RCSR 0x24 /* Receive Command/status Register */ macro
505 * Receive status Bits in Receive Command/status Register RCSR
522 #define usc_UnlatchRxstatusBits(a,b) usc_OutReg( (a), RCSR, (u16)((b) & RXSTATUS_ALL) )
681 #define usc_RCmd(a,b) usc_OutReg((a), RCSR, (b))
1162 * interrupt is indicated by the state of the RCSR.
1170 u16 status = usc_InReg( info, RCSR );
1474 status = usc_InReg(info, RCSR);
3546 u16 Rscr = usc_InReg( info, RCSR );
6107 if (usc_InReg( info, RCSR ) & (BIT8 + BIT4 + BIT3 + BIT1))
|
| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/char/ |
| H A D | synclink.c | 362 #define RCSR 0x24 /* Receive Command/status Register */ macro
505 * Receive status Bits in Receive Command/status Register RCSR
522 #define usc_UnlatchRxstatusBits(a,b) usc_OutReg( (a), RCSR, (u16)((b) & RXSTATUS_ALL) )
681 #define usc_RCmd(a,b) usc_OutReg((a), RCSR, (b))
1162 * interrupt is indicated by the state of the RCSR.
1170 u16 status = usc_InReg( info, RCSR );
1474 status = usc_InReg(info, RCSR);
3546 u16 Rscr = usc_InReg( info, RCSR );
6107 if (usc_InReg( info, RCSR ) & (BIT8 + BIT4 + BIT3 + BIT1))
|
Completed in 402 milliseconds