Searched refs:Q_ADDR (Results 1 - 8 of 8) sorted by relevance

/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/net/
H A Dsky2.c999 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
1000 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
1001 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
1002 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
1198 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1229 sky2_write32(hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1232 sky2_write32(hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1262 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1449 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1455 sky2_write32(hw, Q_ADDR(rx
[all...]
H A Dskge.c2521 skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET);
2522 skge_write32(hw, Q_ADDR(q, Q_F), watermark);
2523 skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32));
2524 skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base);
2598 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);
2622 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP);
2625 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET);
2659 skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP);
2673 skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET);
2789 skge_write8(hw, Q_ADDR(txqadd
[all...]
H A Dsky2.h725 /* Queue Register Offsets, use Q_ADDR() to access */
749 #define Q_ADDR(reg, offs) (B8_Q_REGS + (reg) + (offs)) macro
H A Dskge.h460 /* Queue Register Offsets, use Q_ADDR() to access */
480 #define Q_ADDR(reg, offs) (B8_Q_REGS + (reg) + (offs)) macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/net/
H A Dsky2.c999 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
1000 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
1001 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
1002 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
1198 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1229 sky2_write32(hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1232 sky2_write32(hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1262 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1449 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1455 sky2_write32(hw, Q_ADDR(rx
[all...]
H A Dskge.c2521 skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET);
2522 skge_write32(hw, Q_ADDR(q, Q_F), watermark);
2523 skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32));
2524 skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base);
2598 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);
2622 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP);
2625 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET);
2659 skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP);
2673 skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET);
2789 skge_write8(hw, Q_ADDR(txqadd
[all...]
H A Dsky2.h725 /* Queue Register Offsets, use Q_ADDR() to access */
749 #define Q_ADDR(reg, offs) (B8_Q_REGS + (reg) + (offs)) macro
H A Dskge.h460 /* Queue Register Offsets, use Q_ADDR() to access */
480 #define Q_ADDR(reg, offs) (B8_Q_REGS + (reg) + (offs)) macro

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