Searched refs:PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 (Results 1 - 9 of 9) sorted by relevance

/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/mips/pci/
H A Dops-bcm63xx.c321 tmp &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM0;
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/mips/pci/
H A Dops-bcm63xx.c321 tmp &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM0;
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/pci/
H A Dsetup-bus.c576 if (!(ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0)) {
577 ctrl |= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0;
587 if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) {
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/pci/
H A Dsetup-bus.c576 if (!(ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0)) {
577 ctrl |= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0;
587 if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) {
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/include/linux/
H A Dpci_regs.h187 #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 /* Prefetch enable for both memory regions */ macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/include/linux/
H A Dpci_regs.h187 #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 /* Prefetch enable for both memory regions */ macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/toolchains/hndtools-arm-linux-2.6.36-uclibc-4.5.3/usr/include/linux/
H A Dpci_regs.h187 #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 /* Prefetch enable for both memory regions */ macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/toolchains/hndtools-arm-linux-2.6.36-uclibc-4.5.3/arm-brcm-linux-uclibcgnueabi/sysroot/usr/include/linux/
H A Dpci_regs.h187 #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 /* Prefetch enable for both memory regions */ macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/toolchains/hndtools-arm-linux-2.6.36-uclibc-4.5.3/arm-linux/sysroot/usr/include/linux/
H A Dpci_regs.h187 #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 /* Prefetch enable for both memory regions */ macro

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