Searched refs:PA_FPGA (Results 1 - 8 of 8) sorted by relevance

/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/sh/include/mach-common/mach/
H A Dsdk7780.h36 #define PA_FPGA (PA_PERIPHERAL + 0x01000000) macro
41 #define FPGA_SRSTR (PA_FPGA + 0x000) /* System reset */
42 #define FPGA_IRQ0SR (PA_FPGA + 0x010) /* IRQ0 status */
43 #define FPGA_IRQ0MR (PA_FPGA + 0x020) /* IRQ0 mask */
44 #define FPGA_BDMR (PA_FPGA + 0x030) /* Board operating mode */
45 #define FPGA_INTT0PRTR (PA_FPGA + 0x040) /* Interrupt test mode0 port */
46 #define FPGA_INTT0SELR (PA_FPGA + 0x050) /* Int. test mode0 select */
47 #define FPGA_INTT1POLR (PA_FPGA + 0x060) /* Int. test mode0 polarity */
48 #define FPGA_NMIR (PA_FPGA + 0x070) /* NMI source */
49 #define FPGA_NMIMR (PA_FPGA
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/sh/include/mach-common/mach/
H A Dsdk7780.h36 #define PA_FPGA (PA_PERIPHERAL + 0x01000000) macro
41 #define FPGA_SRSTR (PA_FPGA + 0x000) /* System reset */
42 #define FPGA_IRQ0SR (PA_FPGA + 0x010) /* IRQ0 status */
43 #define FPGA_IRQ0MR (PA_FPGA + 0x020) /* IRQ0 mask */
44 #define FPGA_BDMR (PA_FPGA + 0x030) /* Board operating mode */
45 #define FPGA_INTT0PRTR (PA_FPGA + 0x040) /* Interrupt test mode0 port */
46 #define FPGA_INTT0SELR (PA_FPGA + 0x050) /* Int. test mode0 select */
47 #define FPGA_INTT1POLR (PA_FPGA + 0x060) /* Int. test mode0 polarity */
48 #define FPGA_NMIR (PA_FPGA + 0x070) /* NMI source */
49 #define FPGA_NMIMR (PA_FPGA
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/sh/include/mach-se/mach/
H A Dse7780.h49 #define PA_FPGA (PA_PERIPHERAL + 0x03000000) /* FPGA base address */ macro
52 #define FPGA_SFTRST (PA_FPGA + 0) /* Soft reset register */
53 #define FPGA_INTMSK1 (PA_FPGA + 2) /* Interrupt Mask register 1 */
54 #define FPGA_INTMSK2 (PA_FPGA + 4) /* Interrupt Mask register 2 */
55 #define FPGA_INTSEL1 (PA_FPGA + 6) /* Interrupt select register 1 */
56 #define FPGA_INTSEL2 (PA_FPGA + 8) /* Interrupt select register 2 */
57 #define FPGA_INTSEL3 (PA_FPGA + 10) /* Interrupt select register 3 */
58 #define FPGA_PCI_INTSEL1 (PA_FPGA + 12) /* PCI Interrupt select register 1 */
59 #define FPGA_PCI_INTSEL2 (PA_FPGA + 14) /* PCI Interrupt select register 2 */
60 #define FPGA_INTSET (PA_FPGA
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H A Dse7721.h52 #define PA_FPGA 0xB7000000 /* FPGA base address */ macro
56 #define FPGA_ILSR1 (PA_FPGA + 0x02)
57 #define FPGA_ILSR2 (PA_FPGA + 0x03)
58 #define FPGA_ILSR3 (PA_FPGA + 0x04)
59 #define FPGA_ILSR4 (PA_FPGA + 0x05)
60 #define FPGA_ILSR5 (PA_FPGA + 0x06)
61 #define FPGA_ILSR6 (PA_FPGA + 0x07)
62 #define FPGA_ILSR7 (PA_FPGA + 0x08)
63 #define FPGA_ILSR8 (PA_FPGA + 0x09)
H A Dse7722.h54 #define PA_FPGA (PA_PERIPHERAL + 0x01800000) /* FPGA base address */ macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/sh/include/mach-se/mach/
H A Dse7780.h49 #define PA_FPGA (PA_PERIPHERAL + 0x03000000) /* FPGA base address */ macro
52 #define FPGA_SFTRST (PA_FPGA + 0) /* Soft reset register */
53 #define FPGA_INTMSK1 (PA_FPGA + 2) /* Interrupt Mask register 1 */
54 #define FPGA_INTMSK2 (PA_FPGA + 4) /* Interrupt Mask register 2 */
55 #define FPGA_INTSEL1 (PA_FPGA + 6) /* Interrupt select register 1 */
56 #define FPGA_INTSEL2 (PA_FPGA + 8) /* Interrupt select register 2 */
57 #define FPGA_INTSEL3 (PA_FPGA + 10) /* Interrupt select register 3 */
58 #define FPGA_PCI_INTSEL1 (PA_FPGA + 12) /* PCI Interrupt select register 1 */
59 #define FPGA_PCI_INTSEL2 (PA_FPGA + 14) /* PCI Interrupt select register 2 */
60 #define FPGA_INTSET (PA_FPGA
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H A Dse7721.h52 #define PA_FPGA 0xB7000000 /* FPGA base address */ macro
56 #define FPGA_ILSR1 (PA_FPGA + 0x02)
57 #define FPGA_ILSR2 (PA_FPGA + 0x03)
58 #define FPGA_ILSR3 (PA_FPGA + 0x04)
59 #define FPGA_ILSR4 (PA_FPGA + 0x05)
60 #define FPGA_ILSR5 (PA_FPGA + 0x06)
61 #define FPGA_ILSR6 (PA_FPGA + 0x07)
62 #define FPGA_ILSR7 (PA_FPGA + 0x08)
63 #define FPGA_ILSR8 (PA_FPGA + 0x09)
H A Dse7722.h54 #define PA_FPGA (PA_PERIPHERAL + 0x01800000) /* FPGA base address */ macro

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