Searched refs:OFF_SS_PC (Results 1 - 3 of 3) sorted by relevance

/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt/router/gdb/opcodes/
H A Dtic80-opc.c429 #define OFF_SS_PC (REG_FPA + 1)
434 #define OFF_SL_PC (OFF_SS_PC + 1)
612 {"br", OP_SI(0x48), 0xFFFF8000, 0, {OFF_SS_PC} },
615 {"br.a", OP_SI(0x49), 0xFFFF8000, 0, {OFF_SS_PC} },
660 {"bbo", OP_SI(0x4A), MASK_SI, 0, {OFF_SS_PC, REG_22, BITNUM} },
666 {"bbo.a", OP_SI(0x4B), MASK_SI, 0, {OFF_SS_PC, REG_22, BITNUM} },
672 {"bbz", OP_SI(0x48), MASK_SI, 0, {OFF_SS_PC, REG_22, BITNUM} },
678 {"bbz.a", OP_SI(0x49), MASK_SI, 0, {OFF_SS_PC, REG_22, BITNUM} },
684 {"bcnd", OP_SI(0x4C), MASK_SI, 0, {OFF_SS_PC, REG_22, CC} },
690 {"bcnd.a", OP_SI(0x4D), MASK_SI, 0, {OFF_SS_PC, REG_2
427 #define OFF_SS_PC macro
[all...]
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src/router/gdb/opcodes/
H A Dtic80-opc.c429 #define OFF_SS_PC (REG_FPA + 1)
434 #define OFF_SL_PC (OFF_SS_PC + 1)
612 {"br", OP_SI(0x48), 0xFFFF8000, 0, {OFF_SS_PC} },
615 {"br.a", OP_SI(0x49), 0xFFFF8000, 0, {OFF_SS_PC} },
660 {"bbo", OP_SI(0x4A), MASK_SI, 0, {OFF_SS_PC, REG_22, BITNUM} },
666 {"bbo.a", OP_SI(0x4B), MASK_SI, 0, {OFF_SS_PC, REG_22, BITNUM} },
672 {"bbz", OP_SI(0x48), MASK_SI, 0, {OFF_SS_PC, REG_22, BITNUM} },
678 {"bbz.a", OP_SI(0x49), MASK_SI, 0, {OFF_SS_PC, REG_22, BITNUM} },
684 {"bcnd", OP_SI(0x4C), MASK_SI, 0, {OFF_SS_PC, REG_22, CC} },
690 {"bcnd.a", OP_SI(0x4D), MASK_SI, 0, {OFF_SS_PC, REG_2
427 #define OFF_SS_PC macro
[all...]
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/router/gdb/opcodes/
H A Dtic80-opc.c429 #define OFF_SS_PC (REG_FPA + 1)
434 #define OFF_SL_PC (OFF_SS_PC + 1)
612 {"br", OP_SI(0x48), 0xFFFF8000, 0, {OFF_SS_PC} },
615 {"br.a", OP_SI(0x49), 0xFFFF8000, 0, {OFF_SS_PC} },
660 {"bbo", OP_SI(0x4A), MASK_SI, 0, {OFF_SS_PC, REG_22, BITNUM} },
666 {"bbo.a", OP_SI(0x4B), MASK_SI, 0, {OFF_SS_PC, REG_22, BITNUM} },
672 {"bbz", OP_SI(0x48), MASK_SI, 0, {OFF_SS_PC, REG_22, BITNUM} },
678 {"bbz.a", OP_SI(0x49), MASK_SI, 0, {OFF_SS_PC, REG_22, BITNUM} },
684 {"bcnd", OP_SI(0x4C), MASK_SI, 0, {OFF_SS_PC, REG_22, CC} },
690 {"bcnd.a", OP_SI(0x4D), MASK_SI, 0, {OFF_SS_PC, REG_2
427 #define OFF_SS_PC macro
[all...]

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