Searched refs:NV04_PFIFO_CACHE1_DMA_CTL (Results 1 - 8 of 8) sorted by relevance

/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/gpu/drm/nouveau/
H A Dnv04_fifo.c198 tmp = nv_rd32(chan->dev, NV04_PFIFO_CACHE1_DMA_CTL) & ~(1 << 31);
199 nv_wr32(chan->dev, NV04_PFIFO_CACHE1_DMA_CTL, tmp);
H A Dnv10_fifo.c133 tmp = nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_CTL) & ~(1 << 31);
134 nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_CTL, tmp);
H A Dnv40_fifo.c144 tmp = nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_CTL) & ~(1 << 31);
145 nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_CTL, tmp);
H A Dnouveau_reg.h547 #define NV04_PFIFO_CACHE1_DMA_CTL 0x00003230 macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/gpu/drm/nouveau/
H A Dnv04_fifo.c198 tmp = nv_rd32(chan->dev, NV04_PFIFO_CACHE1_DMA_CTL) & ~(1 << 31);
199 nv_wr32(chan->dev, NV04_PFIFO_CACHE1_DMA_CTL, tmp);
H A Dnv10_fifo.c133 tmp = nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_CTL) & ~(1 << 31);
134 nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_CTL, tmp);
H A Dnv40_fifo.c144 tmp = nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_CTL) & ~(1 << 31);
145 nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_CTL, tmp);
H A Dnouveau_reg.h547 #define NV04_PFIFO_CACHE1_DMA_CTL 0x00003230 macro

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