Searched refs:NV03_PFIFO_CACHE1_PUSH1 (Results 1 - 10 of 10) sorted by relevance
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/gpu/drm/nouveau/ |
H A D | nv04_fifo.c | 111 return nv_rd32(dev, NV03_PFIFO_CACHE1_PUSH1) & 192 nv_wr32(chan->dev, NV03_PFIFO_CACHE1_PUSH1, 234 nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH1, pfifo->channels - 1); 291 nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH1, pfifo->channels - 1);
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H A D | nv10_fifo.c | 37 return nv_rd32(dev, NV03_PFIFO_CACHE1_PUSH1) & 128 nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH1, 175 nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH1, pfifo->channels - 1); 235 nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH1, pfifo->channels - 1);
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H A D | nv40_fifo.c | 139 nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH1, 193 nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH1, 292 nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH1, pfifo->channels - 1);
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H A D | nv50_fifo.c | 213 return nv_rd32(dev, NV03_PFIFO_CACHE1_PUSH1) & 377 nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH1, chan->id | (1<<16)); 462 nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH1, 127);
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H A D | nouveau_reg.h | 475 #define NV03_PFIFO_CACHE1_PUSH1 0x00003204 macro
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/gpu/drm/nouveau/ |
H A D | nv04_fifo.c | 111 return nv_rd32(dev, NV03_PFIFO_CACHE1_PUSH1) & 192 nv_wr32(chan->dev, NV03_PFIFO_CACHE1_PUSH1, 234 nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH1, pfifo->channels - 1); 291 nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH1, pfifo->channels - 1);
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H A D | nv10_fifo.c | 37 return nv_rd32(dev, NV03_PFIFO_CACHE1_PUSH1) & 128 nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH1, 175 nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH1, pfifo->channels - 1); 235 nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH1, pfifo->channels - 1);
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H A D | nv40_fifo.c | 139 nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH1, 193 nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH1, 292 nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH1, pfifo->channels - 1);
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H A D | nv50_fifo.c | 213 return nv_rd32(dev, NV03_PFIFO_CACHE1_PUSH1) & 377 nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH1, chan->id | (1<<16)); 462 nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH1, 127);
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H A D | nouveau_reg.h | 475 #define NV03_PFIFO_CACHE1_PUSH1 0x00003204 macro
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