Searched refs:MXVR_CLK_CTL (Results 1 - 4 of 4) sorted by relevance

/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/blackfin/mach-bf548/include/mach/
H A DdefBF549.h185 #define MXVR_CLK_CTL 0xffc028d0 /* MXVR Clock Control Register */ macro
H A DcdefBF549.h299 #define bfin_read_MXVR_CLK_CTL() bfin_read32(MXVR_CLK_CTL)
300 #define bfin_write_MXVR_CLK_CTL(val) bfin_write32(MXVR_CLK_CTL, val)
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/blackfin/mach-bf548/include/mach/
H A DdefBF549.h185 #define MXVR_CLK_CTL 0xffc028d0 /* MXVR Clock Control Register */ macro
H A DcdefBF549.h299 #define bfin_read_MXVR_CLK_CTL() bfin_read32(MXVR_CLK_CTL)
300 #define bfin_write_MXVR_CLK_CTL(val) bfin_write32(MXVR_CLK_CTL, val)

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