Searched refs:MXC_PLL_DP_CTL (Results 1 - 8 of 8) sorted by relevance

/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mach-mx5/
H A Dclock-mx51.c120 dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL);
185 dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL);
187 __raw_writel(dp_ctl | 0x1000L, pllbase + MXC_PLL_DP_CTL);
211 reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) | MXC_PLL_DP_CTL_UPEN;
212 __raw_writel(reg, pllbase + MXC_PLL_DP_CTL);
216 reg = __raw_readl(pllbase + MXC_PLL_DP_CTL);
237 reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) & ~MXC_PLL_DP_CTL_UPEN;
238 __raw_writel(reg, pllbase + MXC_PLL_DP_CTL);
H A Dcrm_regs.h22 #define MXC_PLL_DP_CTL 0x00 macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-mx5/
H A Dclock-mx51.c120 dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL);
185 dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL);
187 __raw_writel(dp_ctl | 0x1000L, pllbase + MXC_PLL_DP_CTL);
211 reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) | MXC_PLL_DP_CTL_UPEN;
212 __raw_writel(reg, pllbase + MXC_PLL_DP_CTL);
216 reg = __raw_readl(pllbase + MXC_PLL_DP_CTL);
237 reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) & ~MXC_PLL_DP_CTL_UPEN;
238 __raw_writel(reg, pllbase + MXC_PLL_DP_CTL);
H A Dcrm_regs.h22 #define MXC_PLL_DP_CTL 0x00 macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mach-mxc91231/
H A Dcrm_regs.h30 #define MXC_PLL_DP_CTL 0x00 macro
H A Dclock.c157 pll_hfsm = __raw_readl(pllbase + MXC_PLL_DP_CTL) & MXC_PLL_DP_CTL_HFSM;
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-mxc91231/
H A Dcrm_regs.h30 #define MXC_PLL_DP_CTL 0x00 macro
H A Dclock.c157 pll_hfsm = __raw_readl(pllbase + MXC_PLL_DP_CTL) & MXC_PLL_DP_CTL_HFSM;

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