Searched refs:MSC01E_INT_SW0 (Results 1 - 4 of 4) sorted by relevance

/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/mips/include/asm/mips-boards/
H A Dmaltaint.h65 #define MSC01E_INT_SW0 1 macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/mips/include/asm/mips-boards/
H A Dmaltaint.h65 #define MSC01E_INT_SW0 1 macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/mips/mti-malta/
H A Dmalta-int.c366 {MSC01E_INT_SW0, MSC01_IRQ_LEVEL, 0},
600 set_vi_handler (MSC01E_INT_SW0, ipi_resched_dispatch);
602 cpu_ipi_resched_irq = MSC01E_INT_SW0;
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/mips/mti-malta/
H A Dmalta-int.c366 {MSC01E_INT_SW0, MSC01_IRQ_LEVEL, 0},
600 set_vi_handler (MSC01E_INT_SW0, ipi_resched_dispatch);
602 cpu_ipi_resched_irq = MSC01E_INT_SW0;

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