Searched refs:MSC01E_INT_CPUCTR (Results 1 - 10 of 10) sorted by relevance

/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/mips/include/asm/mips-boards/
H A Dsimint.h29 #define MSC01E_INT_CPUCTR 11 macro
H A Dmaltaint.h79 #define MSC01E_INT_CPUCTR 11 macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/mips/include/asm/mips-boards/
H A Dsimint.h29 #define MSC01E_INT_CPUCTR 11 macro
H A Dmaltaint.h79 #define MSC01E_INT_CPUCTR 11 macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/mips/mipssim/
H A Dsim_time.c68 set_vi_handler(MSC01E_INT_CPUCTR, mips_timer_dispatch);
69 mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR;
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/mips/mipssim/
H A Dsim_time.c68 set_vi_handler(MSC01E_INT_CPUCTR, mips_timer_dispatch);
69 mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR;
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/mips/mti-malta/
H A Dmalta-time.c132 set_vi_handler(MSC01E_INT_CPUCTR, mips_timer_dispatch);
133 mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR;
H A Dmalta-int.c375 {MSC01E_INT_CPUCTR, MSC01_IRQ_LEVEL, 0}
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/mips/mti-malta/
H A Dmalta-time.c132 set_vi_handler(MSC01E_INT_CPUCTR, mips_timer_dispatch);
133 mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR;
H A Dmalta-int.c375 {MSC01E_INT_CPUCTR, MSC01_IRQ_LEVEL, 0}

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