Searched refs:MOD_EXP_CTIME_MIN_CACHE_LINE_WIDTH (Results 1 - 12 of 12) sorted by relevance

/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src/router/openssl-1.0.0q/crypto/bn/
H A Dbn_lcl.h170 #define MOD_EXP_CTIME_MIN_CACHE_LINE_WIDTH ( 64 ) macro
171 #define MOD_EXP_CTIME_MIN_CACHE_LINE_MASK (MOD_EXP_CTIME_MIN_CACHE_LINE_WIDTH - 1)
178 * log_2(MOD_EXP_CTIME_MIN_CACHE_LINE_WIDTH).
185 #if MOD_EXP_CTIME_MIN_CACHE_LINE_WIDTH == 64
194 #elif MOD_EXP_CTIME_MIN_CACHE_LINE_WIDTH == 32
H A Dbn_exp.c564 ((unsigned char*)(x_) + (MOD_EXP_CTIME_MIN_CACHE_LINE_WIDTH - (((BN_ULONG)(x_)) & (MOD_EXP_CTIME_MIN_CACHE_LINE_MASK))))
629 if ((powerbufFree=(unsigned char*)OPENSSL_malloc(powerbufLen+MOD_EXP_CTIME_MIN_CACHE_LINE_WIDTH)) == NULL)
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src/router/openssl/crypto/bn/
H A Dbn_lcl.h168 # define MOD_EXP_CTIME_MIN_CACHE_LINE_WIDTH ( 64 ) macro
169 # define MOD_EXP_CTIME_MIN_CACHE_LINE_MASK (MOD_EXP_CTIME_MIN_CACHE_LINE_WIDTH - 1)
175 * log_2(MOD_EXP_CTIME_MIN_CACHE_LINE_WIDTH). Window size thresholds are
180 # if MOD_EXP_CTIME_MIN_CACHE_LINE_WIDTH == 64
189 # elif MOD_EXP_CTIME_MIN_CACHE_LINE_WIDTH == 32
H A Dbn_exp.c635 ((unsigned char*)(x_) + (MOD_EXP_CTIME_MIN_CACHE_LINE_WIDTH - (((size_t)(x_)) & (MOD_EXP_CTIME_MIN_CACHE_LINE_MASK))))
751 alloca(powerbufLen + MOD_EXP_CTIME_MIN_CACHE_LINE_WIDTH);
756 MOD_EXP_CTIME_MIN_CACHE_LINE_WIDTH))
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt/router/openssl-1.0.0q/crypto/bn/
H A Dbn_lcl.h170 #define MOD_EXP_CTIME_MIN_CACHE_LINE_WIDTH ( 64 ) macro
171 #define MOD_EXP_CTIME_MIN_CACHE_LINE_MASK (MOD_EXP_CTIME_MIN_CACHE_LINE_WIDTH - 1)
178 * log_2(MOD_EXP_CTIME_MIN_CACHE_LINE_WIDTH).
185 #if MOD_EXP_CTIME_MIN_CACHE_LINE_WIDTH == 64
194 #elif MOD_EXP_CTIME_MIN_CACHE_LINE_WIDTH == 32
H A Dbn_exp.c564 ((unsigned char*)(x_) + (MOD_EXP_CTIME_MIN_CACHE_LINE_WIDTH - (((BN_ULONG)(x_)) & (MOD_EXP_CTIME_MIN_CACHE_LINE_MASK))))
629 if ((powerbufFree=(unsigned char*)OPENSSL_malloc(powerbufLen+MOD_EXP_CTIME_MIN_CACHE_LINE_WIDTH)) == NULL)
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt/router/openssl/crypto/bn/
H A Dbn_lcl.h168 # define MOD_EXP_CTIME_MIN_CACHE_LINE_WIDTH ( 64 ) macro
169 # define MOD_EXP_CTIME_MIN_CACHE_LINE_MASK (MOD_EXP_CTIME_MIN_CACHE_LINE_WIDTH - 1)
175 * log_2(MOD_EXP_CTIME_MIN_CACHE_LINE_WIDTH). Window size thresholds are
180 # if MOD_EXP_CTIME_MIN_CACHE_LINE_WIDTH == 64
189 # elif MOD_EXP_CTIME_MIN_CACHE_LINE_WIDTH == 32
H A Dbn_exp.c635 ((unsigned char*)(x_) + (MOD_EXP_CTIME_MIN_CACHE_LINE_WIDTH - (((size_t)(x_)) & (MOD_EXP_CTIME_MIN_CACHE_LINE_MASK))))
751 alloca(powerbufLen + MOD_EXP_CTIME_MIN_CACHE_LINE_WIDTH);
756 MOD_EXP_CTIME_MIN_CACHE_LINE_WIDTH))
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/router/openssl-1.0.0q/crypto/bn/
H A Dbn_lcl.h170 #define MOD_EXP_CTIME_MIN_CACHE_LINE_WIDTH ( 64 ) macro
171 #define MOD_EXP_CTIME_MIN_CACHE_LINE_MASK (MOD_EXP_CTIME_MIN_CACHE_LINE_WIDTH - 1)
178 * log_2(MOD_EXP_CTIME_MIN_CACHE_LINE_WIDTH).
185 #if MOD_EXP_CTIME_MIN_CACHE_LINE_WIDTH == 64
194 #elif MOD_EXP_CTIME_MIN_CACHE_LINE_WIDTH == 32
H A Dbn_exp.c564 ((unsigned char*)(x_) + (MOD_EXP_CTIME_MIN_CACHE_LINE_WIDTH - (((BN_ULONG)(x_)) & (MOD_EXP_CTIME_MIN_CACHE_LINE_MASK))))
629 if ((powerbufFree=(unsigned char*)OPENSSL_malloc(powerbufLen+MOD_EXP_CTIME_MIN_CACHE_LINE_WIDTH)) == NULL)
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/router/openssl/crypto/bn/
H A Dbn_lcl.h168 # define MOD_EXP_CTIME_MIN_CACHE_LINE_WIDTH ( 64 ) macro
169 # define MOD_EXP_CTIME_MIN_CACHE_LINE_MASK (MOD_EXP_CTIME_MIN_CACHE_LINE_WIDTH - 1)
175 * log_2(MOD_EXP_CTIME_MIN_CACHE_LINE_WIDTH). Window size thresholds are
180 # if MOD_EXP_CTIME_MIN_CACHE_LINE_WIDTH == 64
189 # elif MOD_EXP_CTIME_MIN_CACHE_LINE_WIDTH == 32
H A Dbn_exp.c635 ((unsigned char*)(x_) + (MOD_EXP_CTIME_MIN_CACHE_LINE_WIDTH - (((size_t)(x_)) & (MOD_EXP_CTIME_MIN_CACHE_LINE_MASK))))
751 alloca(powerbufLen + MOD_EXP_CTIME_MIN_CACHE_LINE_WIDTH);
756 MOD_EXP_CTIME_MIN_CACHE_LINE_WIDTH))

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