Searched refs:MIPS_CPU_IRQ_BASE (Results 1 - 25 of 110) sorted by relevance

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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/mips/include/asm/mach-cobalt/
H A Dirq.h40 #define MIPS_CPU_IRQ_BASE 16 macro
42 #define GT641XX_CASCADE_IRQ (MIPS_CPU_IRQ_BASE + 2)
43 #define RAQ2_SCSI_IRQ (MIPS_CPU_IRQ_BASE + 3)
44 #define ETH0_IRQ (MIPS_CPU_IRQ_BASE + 3)
45 #define QUBE1_ETH0_IRQ (MIPS_CPU_IRQ_BASE + 4)
46 #define ETH1_IRQ (MIPS_CPU_IRQ_BASE + 4)
47 #define SERIAL_IRQ (MIPS_CPU_IRQ_BASE + 5)
48 #define SCSI_IRQ (MIPS_CPU_IRQ_BASE + 5)
49 #define I8259_CASCADE_IRQ (MIPS_CPU_IRQ_BASE + 6)
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/mips/include/asm/mach-cobalt/
H A Dirq.h40 #define MIPS_CPU_IRQ_BASE 16 macro
42 #define GT641XX_CASCADE_IRQ (MIPS_CPU_IRQ_BASE + 2)
43 #define RAQ2_SCSI_IRQ (MIPS_CPU_IRQ_BASE + 3)
44 #define ETH0_IRQ (MIPS_CPU_IRQ_BASE + 3)
45 #define QUBE1_ETH0_IRQ (MIPS_CPU_IRQ_BASE + 4)
46 #define ETH1_IRQ (MIPS_CPU_IRQ_BASE + 4)
47 #define SERIAL_IRQ (MIPS_CPU_IRQ_BASE + 5)
48 #define SCSI_IRQ (MIPS_CPU_IRQ_BASE + 5)
49 #define I8259_CASCADE_IRQ (MIPS_CPU_IRQ_BASE + 6)
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/mips/include/asm/mach-generic/
H A Dirq.h23 #ifndef MIPS_CPU_IRQ_BASE
25 #define MIPS_CPU_IRQ_BASE 16 macro
27 #define MIPS_CPU_IRQ_BASE 0 macro
33 #define RM7K_CPU_IRQ_BASE (MIPS_CPU_IRQ_BASE+8)
39 #define RM9K_CPU_IRQ_BASE (MIPS_CPU_IRQ_BASE+12)
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/mips/include/asm/mach-generic/
H A Dirq.h23 #ifndef MIPS_CPU_IRQ_BASE
25 #define MIPS_CPU_IRQ_BASE 16 macro
27 #define MIPS_CPU_IRQ_BASE 0 macro
33 #define RM7K_CPU_IRQ_BASE (MIPS_CPU_IRQ_BASE+8)
39 #define RM9K_CPU_IRQ_BASE (MIPS_CPU_IRQ_BASE+12)
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/mips/include/asm/mach-pnx833x/
H A Dirq.h48 #define MIPS_CPU_IRQ_BASE 0 macro
49 #define PNX833X_PIC_IRQ_BASE (MIPS_CPU_IRQ_BASE + MIPS_CPU_NUM_IRQ)
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/mips/include/asm/mach-pnx833x/
H A Dirq.h48 #define MIPS_CPU_IRQ_BASE 0 macro
49 #define PNX833X_PIC_IRQ_BASE (MIPS_CPU_IRQ_BASE + MIPS_CPU_NUM_IRQ)
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/mips/include/asm/mach-lasat/
H A Dirq.h4 #define LASAT_CASCADE_IRQ (MIPS_CPU_IRQ_BASE + 2)
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/mips/include/asm/mach-powertv/
H A Dirq.h23 #define MIPS_CPU_IRQ_BASE ibase macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/mips/include/asm/mach-lasat/
H A Dirq.h4 #define LASAT_CASCADE_IRQ (MIPS_CPU_IRQ_BASE + 2)
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/mips/include/asm/mach-powertv/
H A Dirq.h23 #define MIPS_CPU_IRQ_BASE ibase macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/mips/loongson/fuloong-2e/
H A Dirq.c31 do_IRQ(MIPS_CPU_IRQ_BASE + 7);
65 setup_irq(MIPS_CPU_IRQ_BASE + 2, &cascade_irqaction);
67 setup_irq(MIPS_CPU_IRQ_BASE + 5, &cascade_irqaction);
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/mips/loongson/fuloong-2e/
H A Dirq.c31 do_IRQ(MIPS_CPU_IRQ_BASE + 7);
65 setup_irq(MIPS_CPU_IRQ_BASE + 2, &cascade_irqaction);
67 setup_irq(MIPS_CPU_IRQ_BASE + 5, &cascade_irqaction);
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/mips/cobalt/
H A Dirq.c37 do_IRQ(MIPS_CPU_IRQ_BASE + 3);
39 do_IRQ(MIPS_CPU_IRQ_BASE + 4);
41 do_IRQ(MIPS_CPU_IRQ_BASE + 5);
43 do_IRQ(MIPS_CPU_IRQ_BASE + 7);
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/mips/include/asm/
H A Dtxx9irq.h15 #define TXX9_IRQ_BASE (MIPS_CPU_IRQ_BASE + 8)
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/mips/cobalt/
H A Dirq.c37 do_IRQ(MIPS_CPU_IRQ_BASE + 3);
39 do_IRQ(MIPS_CPU_IRQ_BASE + 4);
41 do_IRQ(MIPS_CPU_IRQ_BASE + 5);
43 do_IRQ(MIPS_CPU_IRQ_BASE + 7);
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/mips/include/asm/
H A Dtxx9irq.h15 #define TXX9_IRQ_BASE (MIPS_CPU_IRQ_BASE + 8)
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/mips/kernel/
H A Dirq_cpu.c41 set_c0_status(0x100 << (irq - MIPS_CPU_IRQ_BASE));
47 clear_c0_status(0x100 << (irq - MIPS_CPU_IRQ_BASE));
71 clear_c0_cause(0x100 << (irq - MIPS_CPU_IRQ_BASE));
85 clear_c0_cause(0x100 << (irq - MIPS_CPU_IRQ_BASE));
102 int irq_base = MIPS_CPU_IRQ_BASE;
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/mips/kernel/
H A Dirq_cpu.c41 set_c0_status(0x100 << (irq - MIPS_CPU_IRQ_BASE));
47 clear_c0_status(0x100 << (irq - MIPS_CPU_IRQ_BASE));
71 clear_c0_cause(0x100 << (irq - MIPS_CPU_IRQ_BASE));
85 clear_c0_cause(0x100 << (irq - MIPS_CPU_IRQ_BASE));
102 int irq_base = MIPS_CPU_IRQ_BASE;
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/mips/mti-sead3/
H A Dsead3-platform.c27 UART(0x1f000900, MIPS_CPU_IRQ_BASE + 4), /* ttyS0 = USB */
28 UART(0x1f000800, MIPS_CPU_IRQ_BASE + 4), /* ttyS1 = RS232 */
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/mips/mti-sead3/
H A Dsead3-platform.c27 UART(0x1f000900, MIPS_CPU_IRQ_BASE + 4), /* ttyS0 = USB */
28 UART(0x1f000800, MIPS_CPU_IRQ_BASE + 4), /* ttyS1 = RS232 */
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/mips/include/asm/mips-boards/
H A Dsead3int.h61 #define MIPS_GIC_IRQ_BASE (MIPS_CPU_IRQ_BASE + 0)
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/mips/loongson/lemote-2f/
H A Dirq.c21 #define LOONGSON_TIMER_IRQ (MIPS_CPU_IRQ_BASE + 7) /* cpu timer */
22 #define LOONGSON_NORTH_BRIDGE_IRQ (MIPS_CPU_IRQ_BASE + 6) /* bonito */
23 #define LOONGSON_UART_IRQ (MIPS_CPU_IRQ_BASE + 3) /* cpu serial port */
24 #define LOONGSON_SOUTH_BRIDGE_IRQ (MIPS_CPU_IRQ_BASE + 2) /* i8259 */
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/mips/include/asm/mips-boards/
H A Dsead3int.h61 #define MIPS_GIC_IRQ_BASE (MIPS_CPU_IRQ_BASE + 0)
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/mips/loongson/lemote-2f/
H A Dirq.c21 #define LOONGSON_TIMER_IRQ (MIPS_CPU_IRQ_BASE + 7) /* cpu timer */
22 #define LOONGSON_NORTH_BRIDGE_IRQ (MIPS_CPU_IRQ_BASE + 6) /* bonito */
23 #define LOONGSON_UART_IRQ (MIPS_CPU_IRQ_BASE + 3) /* cpu serial port */
24 #define LOONGSON_SOUTH_BRIDGE_IRQ (MIPS_CPU_IRQ_BASE + 2) /* i8259 */
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/mips/txx9/rbtx4938/
H A Dirq.c14 * MIPS_CPU_IRQ_BASE+00 Software 0
15 * MIPS_CPU_IRQ_BASE+01 Software 1
16 * MIPS_CPU_IRQ_BASE+02 Cascade TX4938-CP0
17 * MIPS_CPU_IRQ_BASE+03 Multiplexed -- do not use
18 * MIPS_CPU_IRQ_BASE+04 Multiplexed -- do not use
19 * MIPS_CPU_IRQ_BASE+05 Multiplexed -- do not use
20 * MIPS_CPU_IRQ_BASE+06 Multiplexed -- do not use
21 * MIPS_CPU_IRQ_BASE+07 CPU TIMER
134 irq = MIPS_CPU_IRQ_BASE + 7;
140 irq = MIPS_CPU_IRQ_BASE
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