Searched refs:MII (Results 1 - 9 of 9) sorted by relevance

/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/cfe/cfe/dev/
H A Ddev_tulip.c84 The 21140 driver assumes that the PHY uses a standard MII interface
94 Kendin KS8761 PHY). It also supports an MII interface for
260 enum {SRL, MII, SYM} phy_type; enumerator in enum:tulip_softc::__anon11103
1081 * MII access utility routines
1084 /* MII clock limited to 2.5 MHz, transactions end with MDIO tristated */
1126 * This routine reads a register from the PHY chip using the MII
1182 * This routine writes a register in the PHY chip using the MII
1227 /* The following functions are suitable for all tulips with MII
1570 /* Cogent/Adaptec MII (ANA-6911A). */
1571 sc->phy_type = MII;
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/cris/boot/rescue/
H A Dhead_v10.S152 ;; Start MII clock to make sure it is running when tranceiver is reset
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/cris/boot/rescue/
H A Dhead_v10.S152 ;; Start MII clock to make sure it is running when tranceiver is reset
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/net/tulip/
H A Dde4x5.h28 #define DE4X5_MII iobase+(0x048 << lp->bus) /* MII Interface Register */
425 #define MII_MDI 0x00080000 /* MII Management Data In */
426 #define MII_MDO 0x00060000 /* MII Management Mode/Data Out */
427 #define MII_MRD 0x00040000 /* MII Management Define Read Mode */
428 #define MII_MWR 0x00000000 /* MII Management Define Write Mode */
429 #define MII_MDT 0x00020000 /* MII Management Data Out */
430 #define MII_MDC 0x00010000 /* MII Management Clock */
431 #define MII_RD 0x00004000 /* Read from MII */
432 #define MII_WR 0x00002000 /* Write to MII */
433 #define MII_SEL 0x00000800 /* Select MII whe
838 #define MII macro
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/net/tulip/
H A Dde4x5.h28 #define DE4X5_MII iobase+(0x048 << lp->bus) /* MII Interface Register */
425 #define MII_MDI 0x00080000 /* MII Management Data In */
426 #define MII_MDO 0x00060000 /* MII Management Mode/Data Out */
427 #define MII_MRD 0x00040000 /* MII Management Define Read Mode */
428 #define MII_MWR 0x00000000 /* MII Management Define Write Mode */
429 #define MII_MDT 0x00020000 /* MII Management Data Out */
430 #define MII_MDC 0x00010000 /* MII Management Clock */
431 #define MII_RD 0x00004000 /* Read from MII */
432 #define MII_WR 0x00002000 /* Write to MII */
433 #define MII_SEL 0x00000800 /* Select MII whe
838 #define MII macro
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/cris/arch-v10/kernel/
H A Dhead.S167 ;; Start MII clock to make sure it is running when tranceiver is reset
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/cris/arch-v10/kernel/
H A Dhead.S167 ;; Start MII clock to make sure it is running when tranceiver is reset
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/net/
H A Dmacb.c571 * add that if/when we get our hands on a full-blown MII PHY.
1178 /* Set MII management clock divider */
1203 macb_writel(bp, USRIO, MACB_BIT(MII));
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/net/
H A Dmacb.c571 * add that if/when we get our hands on a full-blown MII PHY.
1178 /* Set MII management clock divider */
1203 macb_writel(bp, USRIO, MACB_BIT(MII));

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