Searched refs:MEM2 (Results 1 - 11 of 11) sorted by relevance

/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/mn10300/mm/
H A Dmisalignment.c162 #define MEM2(ADDR1, ADDR2) (0x80000000 | (ADDR1) << 8 | (ADDR2)) macro
186 { "mov", 0x4200, 0xf300, 0, FMT_S1, 0, {DM1, MEM2(IMM8, SP)}},
187 { "mov", 0x4300, 0xf300, 0, FMT_S1, 0, {AM1, MEM2(IMM8, SP)}},
188 { "mov", 0x5800, 0xfc00, 0, FMT_S1, 0, {MEM2(IMM8, SP), DN0}},
189 { "mov", 0x5c00, 0xfc00, 0, FMT_S1, 0, {MEM2(IMM8, SP), AN0}},
194 { "mov", 0xf300, 0xffc0, 0, FMT_D0, 0, {MEM2(DI, AM0), DN2}},
195 { "mov", 0xf340, 0xffc0, 0, FMT_D0, 0, {DM2, MEM2(DI, AN0)}},
196 { "mov", 0xf380, 0xffc0, 0, FMT_D0, 0, {MEM2(DI, AM0), AN2}},
197 { "mov", 0xf3c0, 0xffc0, 0, FMT_D0, 0, {AM2, MEM2(DI, AN0)}},
198 { "mov", 0xf80000, 0xfff000, 0, FMT_D1, 0, {MEM2(SD
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/mn10300/mm/
H A Dmisalignment.c162 #define MEM2(ADDR1, ADDR2) (0x80000000 | (ADDR1) << 8 | (ADDR2)) macro
186 { "mov", 0x4200, 0xf300, 0, FMT_S1, 0, {DM1, MEM2(IMM8, SP)}},
187 { "mov", 0x4300, 0xf300, 0, FMT_S1, 0, {AM1, MEM2(IMM8, SP)}},
188 { "mov", 0x5800, 0xfc00, 0, FMT_S1, 0, {MEM2(IMM8, SP), DN0}},
189 { "mov", 0x5c00, 0xfc00, 0, FMT_S1, 0, {MEM2(IMM8, SP), AN0}},
194 { "mov", 0xf300, 0xffc0, 0, FMT_D0, 0, {MEM2(DI, AM0), DN2}},
195 { "mov", 0xf340, 0xffc0, 0, FMT_D0, 0, {DM2, MEM2(DI, AN0)}},
196 { "mov", 0xf380, 0xffc0, 0, FMT_D0, 0, {MEM2(DI, AM0), AN2}},
197 { "mov", 0xf3c0, 0xffc0, 0, FMT_D0, 0, {AM2, MEM2(DI, AN0)}},
198 { "mov", 0xf80000, 0xfff000, 0, FMT_D1, 0, {MEM2(SD
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt/router/gdb/opcodes/
H A Dm10200-opc.c146 #define MEM2(ADDR1,ADDR2) PAREN, ADDR1, ADDR2, PAREN
177 { "mov", 0x6000, 0xf000, FMT_2, {MEM2(SD8, AN1), DM0}},
178 { "mov", 0xf7c00000, 0xfff00000, FMT_6, {MEM2(SD16, AN1), DM0}},
179 { "mov", 0xf4800000, 0xfff00000, FMT_7, {MEM2(IMM24,AN1), DM0}},
180 { "mov", 0xf140, 0xffc0, FMT_4, {MEM2(DI, AN1), DM0}},
183 { "mov", 0x7000, 0xf000, FMT_2, {MEM2(SD8,AN1), AM0}},
185 { "mov", 0xf7b00000, 0xfff00000, FMT_6, {MEM2(SD16, AN1), AM0}},
186 { "mov", 0xf4f00000, 0xfff00000, FMT_7, {MEM2(IMM24,AN1), AM0}},
187 { "mov", 0xf100, 0xffc0, FMT_4, {MEM2(DI, AN1), AM0}},
191 { "mov", 0x4000, 0xf000, FMT_2, {DM0, MEM2(SD
145 #define MEM2 macro
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H A Dm10300-opc.c430 #define MEM2(ADDR1,ADDR2) PAREN, ADDR1, ADDR2, PAREN
475 { "mov", 0x5c00, 0xfc00, 0, FMT_S1, 0, {MEM2(IMM8, SP), AN0}},
476 { "mov", 0xf80000, 0xfff000, 0, FMT_D1, 0, {MEM2(SD8, AM0), DN1}},
477 { "mov", 0xfa000000, 0xfff00000, 0, FMT_D2, 0, {MEM2(SD16, AM0), DN1}},
478 { "mov", 0x5800, 0xfc00, 0, FMT_S1, 0, {MEM2(IMM8, SP), DN0}},
479 { "mov", 0xfab40000, 0xfffc0000, 0, FMT_D2, 0, {MEM2(IMM16, SP), DN0}},
480 { "mov", 0xf300, 0xffc0, 0, FMT_D0, 0, {MEM2(DI, AM0), DN2}},
481 { "mov", 0xf82000, 0xfff000, 0, FMT_D1, 0, {MEM2(SD8,AM0), AN1}},
482 { "mov", 0xfa200000, 0xfff00000, 0, FMT_D2, 0, {MEM2(SD16, AM0), AN1}},
483 { "mov", 0xfab00000, 0xfffc0000, 0, FMT_D2, 0, {MEM2(IMM1
429 #define MEM2 macro
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src/router/gdb/opcodes/
H A Dm10200-opc.c146 #define MEM2(ADDR1,ADDR2) PAREN, ADDR1, ADDR2, PAREN
177 { "mov", 0x6000, 0xf000, FMT_2, {MEM2(SD8, AN1), DM0}},
178 { "mov", 0xf7c00000, 0xfff00000, FMT_6, {MEM2(SD16, AN1), DM0}},
179 { "mov", 0xf4800000, 0xfff00000, FMT_7, {MEM2(IMM24,AN1), DM0}},
180 { "mov", 0xf140, 0xffc0, FMT_4, {MEM2(DI, AN1), DM0}},
183 { "mov", 0x7000, 0xf000, FMT_2, {MEM2(SD8,AN1), AM0}},
185 { "mov", 0xf7b00000, 0xfff00000, FMT_6, {MEM2(SD16, AN1), AM0}},
186 { "mov", 0xf4f00000, 0xfff00000, FMT_7, {MEM2(IMM24,AN1), AM0}},
187 { "mov", 0xf100, 0xffc0, FMT_4, {MEM2(DI, AN1), AM0}},
191 { "mov", 0x4000, 0xf000, FMT_2, {DM0, MEM2(SD
145 #define MEM2 macro
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H A Dm10300-opc.c430 #define MEM2(ADDR1,ADDR2) PAREN, ADDR1, ADDR2, PAREN
475 { "mov", 0x5c00, 0xfc00, 0, FMT_S1, 0, {MEM2(IMM8, SP), AN0}},
476 { "mov", 0xf80000, 0xfff000, 0, FMT_D1, 0, {MEM2(SD8, AM0), DN1}},
477 { "mov", 0xfa000000, 0xfff00000, 0, FMT_D2, 0, {MEM2(SD16, AM0), DN1}},
478 { "mov", 0x5800, 0xfc00, 0, FMT_S1, 0, {MEM2(IMM8, SP), DN0}},
479 { "mov", 0xfab40000, 0xfffc0000, 0, FMT_D2, 0, {MEM2(IMM16, SP), DN0}},
480 { "mov", 0xf300, 0xffc0, 0, FMT_D0, 0, {MEM2(DI, AM0), DN2}},
481 { "mov", 0xf82000, 0xfff000, 0, FMT_D1, 0, {MEM2(SD8,AM0), AN1}},
482 { "mov", 0xfa200000, 0xfff00000, 0, FMT_D2, 0, {MEM2(SD16, AM0), AN1}},
483 { "mov", 0xfab00000, 0xfffc0000, 0, FMT_D2, 0, {MEM2(IMM1
429 #define MEM2 macro
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/router/gdb/opcodes/
H A Dm10200-opc.c146 #define MEM2(ADDR1,ADDR2) PAREN, ADDR1, ADDR2, PAREN
177 { "mov", 0x6000, 0xf000, FMT_2, {MEM2(SD8, AN1), DM0}},
178 { "mov", 0xf7c00000, 0xfff00000, FMT_6, {MEM2(SD16, AN1), DM0}},
179 { "mov", 0xf4800000, 0xfff00000, FMT_7, {MEM2(IMM24,AN1), DM0}},
180 { "mov", 0xf140, 0xffc0, FMT_4, {MEM2(DI, AN1), DM0}},
183 { "mov", 0x7000, 0xf000, FMT_2, {MEM2(SD8,AN1), AM0}},
185 { "mov", 0xf7b00000, 0xfff00000, FMT_6, {MEM2(SD16, AN1), AM0}},
186 { "mov", 0xf4f00000, 0xfff00000, FMT_7, {MEM2(IMM24,AN1), AM0}},
187 { "mov", 0xf100, 0xffc0, FMT_4, {MEM2(DI, AN1), AM0}},
191 { "mov", 0x4000, 0xf000, FMT_2, {DM0, MEM2(SD
145 #define MEM2 macro
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H A Dm10300-opc.c430 #define MEM2(ADDR1,ADDR2) PAREN, ADDR1, ADDR2, PAREN
475 { "mov", 0x5c00, 0xfc00, 0, FMT_S1, 0, {MEM2(IMM8, SP), AN0}},
476 { "mov", 0xf80000, 0xfff000, 0, FMT_D1, 0, {MEM2(SD8, AM0), DN1}},
477 { "mov", 0xfa000000, 0xfff00000, 0, FMT_D2, 0, {MEM2(SD16, AM0), DN1}},
478 { "mov", 0x5800, 0xfc00, 0, FMT_S1, 0, {MEM2(IMM8, SP), DN0}},
479 { "mov", 0xfab40000, 0xfffc0000, 0, FMT_D2, 0, {MEM2(IMM16, SP), DN0}},
480 { "mov", 0xf300, 0xffc0, 0, FMT_D0, 0, {MEM2(DI, AM0), DN2}},
481 { "mov", 0xf82000, 0xfff000, 0, FMT_D1, 0, {MEM2(SD8,AM0), AN1}},
482 { "mov", 0xfa200000, 0xfff00000, 0, FMT_D2, 0, {MEM2(SD16, AM0), AN1}},
483 { "mov", 0xfab00000, 0xfffc0000, 0, FMT_D2, 0, {MEM2(IMM1
429 #define MEM2 macro
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src/router/gdb/include/opcode/
H A Di960.h42 #define MEM2 5 macro
268 { 0x88000000, "ldos", I_BASE, MEM2, 2, { M, R, 0 } },
269 { 0x8a000000, "stos", I_BASE, MEM2, 2, { R, M, 0 } },
281 { 0xc8000000, "ldis", I_BASE, MEM2, 2, { M, R, 0 } },
282 { 0xca000000, "stis", I_BASE, MEM2, 2, { R, M, 0 } },
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt/router/gdb/include/opcode/
H A Di960.h42 #define MEM2 5 macro
268 { 0x88000000, "ldos", I_BASE, MEM2, 2, { M, R, 0 } },
269 { 0x8a000000, "stos", I_BASE, MEM2, 2, { R, M, 0 } },
281 { 0xc8000000, "ldis", I_BASE, MEM2, 2, { M, R, 0 } },
282 { 0xca000000, "stis", I_BASE, MEM2, 2, { R, M, 0 } },
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/router/gdb/include/opcode/
H A Di960.h42 #define MEM2 5 macro
268 { 0x88000000, "ldos", I_BASE, MEM2, 2, { M, R, 0 } },
269 { 0x8a000000, "stos", I_BASE, MEM2, 2, { R, M, 0 } },
281 { 0xc8000000, "ldis", I_BASE, MEM2, 2, { M, R, 0 } },
282 { 0xca000000, "stis", I_BASE, MEM2, 2, { R, M, 0 } },

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