Searched refs:MDREFR (Results 1 - 16 of 16) sorted by relevance
| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mach-sa1100/ |
| H A D | cpu-sa1110.c | 176 sd->mdrefr = MDREFR & 0xffbffff0;
186 printk("MDCNFG: %08x MDREFR: %08x MDCAS0: %08x MDCAS1: %08x MDCAS2: %08x\n",
196 MDREFR = (MDREFR & 0xffff000f) | (dri << 4);
197 (void) MDREFR;
278 str %4, [%1, #28] @ MDREFR \n\
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| H A D | sleep.S | 65 ldr r0, =MDREFR
97 ldr r6, =MDREFR
126 @ Step 2 clear DRI field in MDREFR
129 @ Step 3 set SLFRSH bit in MDREFR
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| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-sa1100/ |
| H A D | cpu-sa1110.c | 176 sd->mdrefr = MDREFR & 0xffbffff0;
186 printk("MDCNFG: %08x MDREFR: %08x MDCAS0: %08x MDCAS1: %08x MDCAS2: %08x\n",
196 MDREFR = (MDREFR & 0xffff000f) | (dri << 4);
197 (void) MDREFR;
278 str %4, [%1, #28] @ MDREFR \n\
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| H A D | sleep.S | 65 ldr r0, =MDREFR
97 ldr r6, =MDREFR
126 @ Step 2 clear DRI field in MDREFR
129 @ Step 3 set SLFRSH bit in MDREFR
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| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mach-pxa/ |
| H A D | cpufreq-pxa2xx.c | 330 /* Calculate the next MDREFR. If we're slowing down the SDRAM clock
334 preset_mdrefr = postset_mdrefr = MDREFR;
335 if ((MDREFR & MDREFR_DRI_MASK) > mdrefr_dri(new_freq_mem)) {
360 ldr r4, [%1] /* load MDREFR */ \n\
364 str %3, [%1] /* preset the MDREFR */ \n\
366 str %4, [%1] /* postset the MDREFR */ \n\
373 : "r" (&MDREFR), "r" (cclkcfg),
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| H A D | h5000.c | 179 MDREFR |= 0x02080000;
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| H A D | pxa27x.c | 257 SAVE(MDREFR);
266 RESTORE(MDREFR);
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| H A D | sleep.S | 188 ldr r4, =MDREFR
239 ldr r4, =MDREFR
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| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-pxa/ |
| H A D | cpufreq-pxa2xx.c | 330 /* Calculate the next MDREFR. If we're slowing down the SDRAM clock
334 preset_mdrefr = postset_mdrefr = MDREFR;
335 if ((MDREFR & MDREFR_DRI_MASK) > mdrefr_dri(new_freq_mem)) {
360 ldr r4, [%1] /* load MDREFR */ \n\
364 str %3, [%1] /* preset the MDREFR */ \n\
366 str %4, [%1] /* postset the MDREFR */ \n\
373 : "r" (&MDREFR), "r" (cclkcfg),
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| H A D | h5000.c | 179 MDREFR |= 0x02080000;
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| H A D | pxa27x.c | 257 SAVE(MDREFR);
266 RESTORE(MDREFR);
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| H A D | sleep.S | 188 ldr r4, =MDREFR
239 ldr r4, =MDREFR
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| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mach-pxa/include/mach/ |
| H A D | pxa2xx-regs.h | 35 #define MDREFR __REG(0x48000004) /* SDRAM Refresh Control Register */ macro
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| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-pxa/include/mach/ |
| H A D | pxa2xx-regs.h | 35 #define MDREFR __REG(0x48000004) /* SDRAM Refresh Control Register */ macro
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| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mach-sa1100/include/mach/ |
| H A D | SA-1100.h | 1559 #define MDREFR __REG(0xA000001C) macro
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| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-sa1100/include/mach/ |
| H A D | SA-1100.h | 1559 #define MDREFR __REG(0xA000001C) macro
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