| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/mn10300/lib/ |
| H A D | __ashrdi3.S | 47 ext d0 # sign-extend result through MDR
|
| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/atm/ |
| H A D | uPD98402.c | 75 PUT((GET(MDR) & ~uPD98402_MDR_SS_MASK) | (set[3] <<
76 uPD98402_MDR_SS_SHIFT),MDR);
102 mode_reg = GET(MDR) & ~(uPD98402_MDR_TPLP | uPD98402_MDR_ALP |
125 PUT(mode_reg,MDR);
|
| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/atm/ |
| H A D | uPD98402.c | 75 PUT((GET(MDR) & ~uPD98402_MDR_SS_MASK) | (set[3] <<
76 uPD98402_MDR_SS_SHIFT),MDR);
102 mode_reg = GET(MDR) & ~(uPD98402_MDR_TPLP | uPD98402_MDR_ALP |
125 PUT(mode_reg,MDR);
|
| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/mn10300/lib/ |
| H A D | __ashrdi3.S | 47 ext d0 # sign-extend result through MDR
|
| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt/router/gdb/opcodes/ |
| H A D | m10200-opc.c | 100 /* MDR register. */ macro
101 #define MDR (PSW+1)
105 #define DI (MDR+1)
174 { "mov", 0xf3e0, 0xfffc, FMT_4, {MDR, DN0}},
175 { "mov", 0xf3c0, 0xfff3, FMT_4, {DN1, MDR}},
|
| H A D | m10300-opc.c | 151 /* MDR register. */ macro
152 #define MDR (PSW+1)
156 #define DI (MDR+1)
461 { "mov", 0xf2e0, 0xfffc, 0, FMT_D0, 0, {MDR, DN0}},
462 { "mov", 0xf2f2, 0xfff3, 0, FMT_D0, 0, {DM1, MDR}},
|
| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src/router/gdb/opcodes/ |
| H A D | m10200-opc.c | 100 /* MDR register. */ macro
101 #define MDR (PSW+1)
105 #define DI (MDR+1)
174 { "mov", 0xf3e0, 0xfffc, FMT_4, {MDR, DN0}},
175 { "mov", 0xf3c0, 0xfff3, FMT_4, {DN1, MDR}},
|
| H A D | m10300-opc.c | 151 /* MDR register. */ macro
152 #define MDR (PSW+1)
156 #define DI (MDR+1)
461 { "mov", 0xf2e0, 0xfffc, 0, FMT_D0, 0, {MDR, DN0}},
462 { "mov", 0xf2f2, 0xfff3, 0, FMT_D0, 0, {DM1, MDR}},
|
| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/router/gdb/opcodes/ |
| H A D | m10200-opc.c | 100 /* MDR register. */ macro
101 #define MDR (PSW+1)
105 #define DI (MDR+1)
174 { "mov", 0xf3e0, 0xfffc, FMT_4, {MDR, DN0}},
175 { "mov", 0xf3c0, 0xfff3, FMT_4, {DN1, MDR}},
|
| H A D | m10300-opc.c | 151 /* MDR register. */ macro
152 #define MDR (PSW+1)
156 #define DI (MDR+1)
461 { "mov", 0xf2e0, 0xfffc, 0, FMT_D0, 0, {MDR, DN0}},
462 { "mov", 0xf2f2, 0xfff3, 0, FMT_D0, 0, {DM1, MDR}},
|