Searched refs:MCFSIM_DMR0 (Results 1 - 16 of 16) sorted by relevance

/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/m68k/include/asm/
H A Dm5206sim.h50 #define MCFSIM_DMR0 0x50 /* DRAM 0 Mask reg (r/w) */ macro
H A Dm5307sim.h89 #define MCFSIM_DMR0 0x10c /* DRAM 0 Mask reg (r/w) */ macro
H A Dm5407sim.h72 #define MCFSIM_DMR0 0x10c /* DRAM 0 Mask reg (r/w) */ macro
H A Dm527xsim.h43 #define MCFSIM_DMR0 0x4c /* SDRAM address mask 0 */ macro
53 #define MCFSIM_DMR0 0x54 /* SDRAM address mask 0 */ macro
H A Dm523xsim.h40 #define MCFSIM_DMR0 0x4c /* SDRAM address mask 0 */ macro
H A Dm5249sim.h55 #define MCFSIM_DMR0 0x10c /* DRAM 0 Mask reg (r/w) */ macro
H A Dm528xsim.h40 #define MCFSIM_DMR0 0x4c /* SDRAM address mask 0 */ macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/m68k/include/asm/
H A Dm5206sim.h50 #define MCFSIM_DMR0 0x50 /* DRAM 0 Mask reg (r/w) */ macro
H A Dm5307sim.h89 #define MCFSIM_DMR0 0x10c /* DRAM 0 Mask reg (r/w) */ macro
H A Dm5407sim.h72 #define MCFSIM_DMR0 0x10c /* DRAM 0 Mask reg (r/w) */ macro
H A Dm527xsim.h43 #define MCFSIM_DMR0 0x4c /* SDRAM address mask 0 */ macro
53 #define MCFSIM_DMR0 0x54 /* SDRAM address mask 0 */ macro
H A Dm523xsim.h40 #define MCFSIM_DMR0 0x4c /* SDRAM address mask 0 */ macro
H A Dm5249sim.h55 #define MCFSIM_DMR0 0x10c /* DRAM 0 Mask reg (r/w) */ macro
H A Dm528xsim.h40 #define MCFSIM_DMR0 0x4c /* SDRAM address mask 0 */ macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/m68knommu/platform/coldfire/
H A Dhead.S44 movel MCF_MBAR+MCFSIM_DMR0,%d0 /* get mask for 1st bank */
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/m68knommu/platform/coldfire/
H A Dhead.S44 movel MCF_MBAR+MCFSIM_DMR0,%d0 /* get mask for 1st bank */

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