Searched refs:MC417_RWD (Results 1 - 10 of 10) sorted by relevance

/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/media/video/cx23885/
H A Dcx23885-417.c223 /**** Bit definitions for MC417_RWD and MC417_OEN registers ***
303 /* Configure MC417_RWD to defaults. */
305 cx_write(MC417_RWD, regval);
314 mi_ready = cx_read(MC417_RWD) & MC417_MIRDY;
335 cx_write(MC417_RWD, regval);
339 cx_write(MC417_RWD, regval);
344 cx_write(MC417_RWD, regval);
346 cx_write(MC417_RWD, regval);
351 cx_write(MC417_RWD, regval);
353 cx_write(MC417_RWD, regva
[all...]
H A Dcimax2.c28 /**** Bit definitions for MC417_RWD and MC417_OEN registers ***
156 mem = cx_read(MC417_RWD);
164 cx_set(MC417_RWD, NETUP_CTRL_OFF);
203 cx_write(MC417_RWD, NETUP_CTRL_OFF |
205 cx_clear(MC417_RWD, NETUP_ADLO);
206 cx_write(MC417_RWD, NETUP_CTRL_OFF |
208 cx_clear(MC417_RWD, NETUP_ADHI);
213 cx_write(MC417_RWD, NETUP_CTRL_OFF | data);
216 cx_clear(MC417_RWD,
219 cx_clear(MC417_RWD, (rea
[all...]
H A Dcx23885-cards.c871 cx_set(MC417_RWD, 0x00000002);
873 cx_clear(MC417_RWD, 0x00000800);
875 cx_set(MC417_RWD, 0x00000800);
900 cx_write(MC417_RWD, 0x0000c300);
H A Dcx23885-reg.h349 #define MC417_RWD 0x00110020 macro
H A Dcx23885-core.c1916 cx_set(MC417_RWD, (mask & 0x0007fff8) >> 3);
1934 cx_clear(MC417_RWD, (mask & 0x7fff8) >> 3);
1952 return (cx_read(MC417_RWD) & ((mask & 0x7fff8) >> 3)) << 3;
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/media/video/cx23885/
H A Dcx23885-417.c223 /**** Bit definitions for MC417_RWD and MC417_OEN registers ***
303 /* Configure MC417_RWD to defaults. */
305 cx_write(MC417_RWD, regval);
314 mi_ready = cx_read(MC417_RWD) & MC417_MIRDY;
335 cx_write(MC417_RWD, regval);
339 cx_write(MC417_RWD, regval);
344 cx_write(MC417_RWD, regval);
346 cx_write(MC417_RWD, regval);
351 cx_write(MC417_RWD, regval);
353 cx_write(MC417_RWD, regva
[all...]
H A Dcimax2.c28 /**** Bit definitions for MC417_RWD and MC417_OEN registers ***
156 mem = cx_read(MC417_RWD);
164 cx_set(MC417_RWD, NETUP_CTRL_OFF);
203 cx_write(MC417_RWD, NETUP_CTRL_OFF |
205 cx_clear(MC417_RWD, NETUP_ADLO);
206 cx_write(MC417_RWD, NETUP_CTRL_OFF |
208 cx_clear(MC417_RWD, NETUP_ADHI);
213 cx_write(MC417_RWD, NETUP_CTRL_OFF | data);
216 cx_clear(MC417_RWD,
219 cx_clear(MC417_RWD, (rea
[all...]
H A Dcx23885-cards.c871 cx_set(MC417_RWD, 0x00000002);
873 cx_clear(MC417_RWD, 0x00000800);
875 cx_set(MC417_RWD, 0x00000800);
900 cx_write(MC417_RWD, 0x0000c300);
H A Dcx23885-reg.h349 #define MC417_RWD 0x00110020 macro
H A Dcx23885-core.c1916 cx_set(MC417_RWD, (mask & 0x0007fff8) >> 3);
1934 cx_clear(MC417_RWD, (mask & 0x7fff8) >> 3);
1952 return (cx_read(MC417_RWD) & ((mask & 0x7fff8) >> 3)) << 3;

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