Searched refs:L1_CACHE_TAG_ENTRY (Results 1 - 4 of 4) sorted by relevance

/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/mn10300/proc-mn103e010/include/proc/
H A Dcache.h24 #define L1_CACHE_TAG_ENTRY 0x00000ff0 /* cache tag entry address mask */ macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/mn10300/proc-mn103e010/include/proc/
H A Dcache.h24 #define L1_CACHE_TAG_ENTRY 0x00000ff0 /* cache tag entry address mask */ macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/mn10300/mm/
H A Dcache-mn10300.S155 and L1_CACHE_TAG_ADDRESS|L1_CACHE_TAG_ENTRY,d0 # round start
160 and L1_CACHE_TAG_ADDRESS|L1_CACHE_TAG_ENTRY,d1
169 and L1_CACHE_TAG_ENTRY,d0
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/mn10300/mm/
H A Dcache-mn10300.S155 and L1_CACHE_TAG_ADDRESS|L1_CACHE_TAG_ENTRY,d0 # round start
160 and L1_CACHE_TAG_ADDRESS|L1_CACHE_TAG_ENTRY,d1
169 and L1_CACHE_TAG_ENTRY,d0

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