Searched refs:L1_CACHE_ALIGN (Results 1 - 25 of 44) sorted by relevance

12

/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/include/linux/
H A Dcache.h7 #ifndef L1_CACHE_ALIGN
8 #define L1_CACHE_ALIGN(x) ALIGN(x, L1_CACHE_BYTES) macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/include/linux/
H A Dcache.h7 #ifndef L1_CACHE_ALIGN
8 #define L1_CACHE_ALIGN(x) ALIGN(x, L1_CACHE_BYTES) macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/ia64/include/asm/
H A Dnodedata.h59 L1_CACHE_ALIGN(sizeof(struct pglist_data))))
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/ia64/include/asm/
H A Dnodedata.h59 L1_CACHE_ALIGN(sizeof(struct pglist_data))))
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/serial/cpm_uart/
H A Dcpm_uart_cpm1.c96 memsz = L1_CACHE_ALIGN(pinfo->rx_nrfifos * pinfo->rx_fifosize) +
97 L1_CACHE_ALIGN(pinfo->tx_nrfifos * pinfo->tx_fifosize);
120 pinfo->tx_buf = pinfo->rx_buf + L1_CACHE_ALIGN(pinfo->rx_nrfifos
131 dma_free_coherent(pinfo->port.dev, L1_CACHE_ALIGN(pinfo->rx_nrfifos *
133 L1_CACHE_ALIGN(pinfo->tx_nrfifos *
H A Dcpm_uart_cpm2.c133 memsz = L1_CACHE_ALIGN(pinfo->rx_nrfifos * pinfo->rx_fifosize) +
134 L1_CACHE_ALIGN(pinfo->tx_nrfifos * pinfo->tx_fifosize);
156 pinfo->tx_buf = pinfo->rx_buf + L1_CACHE_ALIGN(pinfo->rx_nrfifos
167 dma_free_coherent(pinfo->port.dev, L1_CACHE_ALIGN(pinfo->rx_nrfifos *
169 L1_CACHE_ALIGN(pinfo->tx_nrfifos *
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/serial/cpm_uart/
H A Dcpm_uart_cpm1.c96 memsz = L1_CACHE_ALIGN(pinfo->rx_nrfifos * pinfo->rx_fifosize) +
97 L1_CACHE_ALIGN(pinfo->tx_nrfifos * pinfo->tx_fifosize);
120 pinfo->tx_buf = pinfo->rx_buf + L1_CACHE_ALIGN(pinfo->rx_nrfifos
131 dma_free_coherent(pinfo->port.dev, L1_CACHE_ALIGN(pinfo->rx_nrfifos *
133 L1_CACHE_ALIGN(pinfo->tx_nrfifos *
H A Dcpm_uart_cpm2.c133 memsz = L1_CACHE_ALIGN(pinfo->rx_nrfifos * pinfo->rx_fifosize) +
134 L1_CACHE_ALIGN(pinfo->tx_nrfifos * pinfo->tx_fifosize);
156 pinfo->tx_buf = pinfo->rx_buf + L1_CACHE_ALIGN(pinfo->rx_nrfifos
167 dma_free_coherent(pinfo->port.dev, L1_CACHE_ALIGN(pinfo->rx_nrfifos *
169 L1_CACHE_ALIGN(pinfo->tx_nrfifos *
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/parisc/include/asm/
H A Dcache.h27 #define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1)) macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/parisc/include/asm/
H A Dcache.h27 #define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1)) macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/misc/sgi-xp/
H A Dxpc_partition.c48 if ((u64)*base == L1_CACHE_ALIGN((u64)*base))
58 return (void *)L1_CACHE_ALIGN((u64)*base);
96 /* !!! L1_CACHE_ALIGN() is only a sn2-bte_copy requirement */
98 len = L1_CACHE_ALIGN(len);
103 buf_len = L1_CACHE_ALIGN(len);
H A Dxpc.h177 #define XPC_RP_HEADER_SIZE L1_CACHE_ALIGN(sizeof(struct xpc_rsvd_page))
178 #define XPC_RP_VARS_SIZE L1_CACHE_ALIGN(sizeof(struct xpc_vars_sn2))
309 L1_CACHE_ALIGN(sizeof(struct xpc_gp_sn2) * XPC_MAX_NCHANNELS)
324 L1_CACHE_ALIGN(sizeof(struct xpc_openclose_args) * \
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/misc/sgi-xp/
H A Dxpc_partition.c48 if ((u64)*base == L1_CACHE_ALIGN((u64)*base))
58 return (void *)L1_CACHE_ALIGN((u64)*base);
96 /* !!! L1_CACHE_ALIGN() is only a sn2-bte_copy requirement */
98 len = L1_CACHE_ALIGN(len);
103 buf_len = L1_CACHE_ALIGN(len);
H A Dxpc.h177 #define XPC_RP_HEADER_SIZE L1_CACHE_ALIGN(sizeof(struct xpc_rsvd_page))
178 #define XPC_RP_VARS_SIZE L1_CACHE_ALIGN(sizeof(struct xpc_vars_sn2))
309 L1_CACHE_ALIGN(sizeof(struct xpc_gp_sn2) * XPC_MAX_NCHANNELS)
324 L1_CACHE_ALIGN(sizeof(struct xpc_openclose_args) * \
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/scsi/
H A D53c700.h226 #define MSGOUT_OFFSET (L1_CACHE_ALIGN(sizeof(SCRIPT)))
228 #define MSGIN_OFFSET (MSGOUT_OFFSET + L1_CACHE_ALIGN(MSG_ARRAY_SIZE))
230 #define STATUS_OFFSET (MSGIN_OFFSET + L1_CACHE_ALIGN(MSG_ARRAY_SIZE))
232 #define SLOTS_OFFSET (STATUS_OFFSET + L1_CACHE_ALIGN(MSG_ARRAY_SIZE))
234 #define TOTAL_MEM_SIZE (SLOTS_OFFSET + L1_CACHE_ALIGN(sizeof(struct NCR_700_command_slot) * NCR_700_COMMAND_SLOTS_PER_HOST))
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/scsi/
H A D53c700.h226 #define MSGOUT_OFFSET (L1_CACHE_ALIGN(sizeof(SCRIPT)))
228 #define MSGIN_OFFSET (MSGOUT_OFFSET + L1_CACHE_ALIGN(MSG_ARRAY_SIZE))
230 #define STATUS_OFFSET (MSGIN_OFFSET + L1_CACHE_ALIGN(MSG_ARRAY_SIZE))
232 #define SLOTS_OFFSET (STATUS_OFFSET + L1_CACHE_ALIGN(MSG_ARRAY_SIZE))
234 #define TOTAL_MEM_SIZE (SLOTS_OFFSET + L1_CACHE_ALIGN(sizeof(struct NCR_700_command_slot) * NCR_700_COMMAND_SLOTS_PER_HOST))
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/ia64/mm/
H A Ddiscontig.c125 pernodesize += L1_CACHE_ALIGN(sizeof(pg_data_t));
126 pernodesize += L1_CACHE_ALIGN(sizeof(struct ia64_node_data));
127 pernodesize += L1_CACHE_ALIGN(sizeof(pg_data_t));
283 pernode += L1_CACHE_ALIGN(sizeof(pg_data_t));
286 pernode += L1_CACHE_ALIGN(sizeof(struct ia64_node_data));
289 pernode += L1_CACHE_ALIGN(sizeof(pg_data_t));
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/ia64/mm/
H A Ddiscontig.c125 pernodesize += L1_CACHE_ALIGN(sizeof(pg_data_t));
126 pernodesize += L1_CACHE_ALIGN(sizeof(struct ia64_node_data));
127 pernodesize += L1_CACHE_ALIGN(sizeof(pg_data_t));
283 pernode += L1_CACHE_ALIGN(sizeof(pg_data_t));
286 pernode += L1_CACHE_ALIGN(sizeof(struct ia64_node_data));
289 pernode += L1_CACHE_ALIGN(sizeof(pg_data_t));
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/net/fs_enet/
H A Dfs_enet-main.c135 L1_CACHE_ALIGN(PKT_MAXBUF_SIZE),
144 L1_CACHE_ALIGN(PKT_MAXBUF_SIZE),
188 L1_CACHE_ALIGN(PKT_MAXBUF_SIZE),
266 L1_CACHE_ALIGN(PKT_MAXBUF_SIZE),
276 L1_CACHE_ALIGN(PKT_MAXBUF_SIZE),
320 L1_CACHE_ALIGN(PKT_MAXBUF_SIZE),
516 L1_CACHE_ALIGN(PKT_MAXBUF_SIZE),
572 L1_CACHE_ALIGN(PKT_MAXBUF_SIZE),
H A Dfs_enet.h118 #define ENET_RX_FRSIZE L1_CACHE_ALIGN(PKT_MAXBUF_SIZE + ENET_RX_ALIGN - 1)
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/net/fs_enet/
H A Dfs_enet-main.c135 L1_CACHE_ALIGN(PKT_MAXBUF_SIZE),
144 L1_CACHE_ALIGN(PKT_MAXBUF_SIZE),
188 L1_CACHE_ALIGN(PKT_MAXBUF_SIZE),
266 L1_CACHE_ALIGN(PKT_MAXBUF_SIZE),
276 L1_CACHE_ALIGN(PKT_MAXBUF_SIZE),
320 L1_CACHE_ALIGN(PKT_MAXBUF_SIZE),
516 L1_CACHE_ALIGN(PKT_MAXBUF_SIZE),
572 L1_CACHE_ALIGN(PKT_MAXBUF_SIZE),
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/sh/mm/
H A Dcache-sh5.c78 addr = L1_CACHE_ALIGN(aligned_start);
222 aligned_start = L1_CACHE_ALIGN(start);
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/sh/mm/
H A Dcache-sh5.c78 addr = L1_CACHE_ALIGN(aligned_start);
222 aligned_start = L1_CACHE_ALIGN(start);
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/ia64/sn/kernel/
H A Dbte.c286 bteBlock = (char *)L1_CACHE_ALIGN((u64) bteBlock_unaligned);
392 headBteLen = L1_CACHE_ALIGN(len + headBcopySrcOffset);
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/ia64/sn/kernel/
H A Dbte.c286 bteBlock = (char *)L1_CACHE_ALIGN((u64) bteBlock_unaligned);
392 headBteLen = L1_CACHE_ALIGN(len + headBcopySrcOffset);

Completed in 259 milliseconds

12