Searched refs:Index_Writeback_Inv_D (Results 1 - 23 of 23) sorted by relevance

/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src/lzma-loader/
H A Ddecompress.c46 #define Index_Writeback_Inv_D 0x01 macro
76 cache_unroll(start,Index_Writeback_Inv_D);
H A Dhead.S38 #define Index_Writeback_Inv_D 0x01 define
120 3: cache Index_Writeback_Inv_D,0(t0)
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt/lzma-loader/
H A Ddecompress.c46 #define Index_Writeback_Inv_D 0x01 macro
76 cache_unroll(start,Index_Writeback_Inv_D);
H A Dhead.S38 #define Index_Writeback_Inv_D 0x01 define
120 3: cache Index_Writeback_Inv_D,0(t0)
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/lzma-loader/
H A Ddecompress.c46 #define Index_Writeback_Inv_D 0x01 macro
76 cache_unroll(start,Index_Writeback_Inv_D);
H A Dhead.S38 #define Index_Writeback_Inv_D 0x01 define
120 3: cache Index_Writeback_Inv_D,0(t0)
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/mips/include/asm/
H A Dr4kcache.h153 cache_op(Index_Writeback_Inv_D, addr);
396 __BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16)
399 __BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32)
402 __BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 64)
407 __BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 16)
408 __BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 32)
H A Dcacheops.h18 #define Index_Writeback_Inv_D 0x01 macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/mips/include/asm/
H A Dr4kcache.h153 cache_op(Index_Writeback_Inv_D, addr);
396 __BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16)
399 __BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32)
402 __BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 64)
407 __BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 16)
408 __BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 32)
H A Dcacheops.h18 #define Index_Writeback_Inv_D 0x01 macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/mips/include/asm/mach-pnx8550/
H A Dkernel-entry-init.h238 .word CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \
240 .word CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \
242 .word CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \
244 .word CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/mips/include/asm/mach-pnx8550/
H A Dkernel-entry-init.h238 .word CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \
240 .word CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \
242 .word CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \
244 .word CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/mips/txx9/generic/
H A Dsetup.c207 cache_op(Index_Writeback_Inv_D, addr | 0);
208 cache_op(Index_Writeback_Inv_D, addr | 1);
209 cache_op(Index_Writeback_Inv_D, addr | 2);
210 cache_op(Index_Writeback_Inv_D, addr | 3);
256 cache_op(Index_Writeback_Inv_D, addr | 0);
257 cache_op(Index_Writeback_Inv_D, addr | 1);
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/mips/txx9/generic/
H A Dsetup.c207 cache_op(Index_Writeback_Inv_D, addr | 0);
208 cache_op(Index_Writeback_Inv_D, addr | 1);
209 cache_op(Index_Writeback_Inv_D, addr | 2);
210 cache_op(Index_Writeback_Inv_D, addr | 3);
256 cache_op(Index_Writeback_Inv_D, addr | 0);
257 cache_op(Index_Writeback_Inv_D, addr | 1);
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/cfe/cfe/arch/mips/cpu/bcmcore/src/
H A Dbcmcore_l1cache.S356 cache Index_Writeback_Inv_D,0(t1)
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/include/
H A Dmipsinc.h221 #define Index_Writeback_Inv_D 0x01 macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/shared/
H A Dmin_osl.c131 cache_op(start, Index_Writeback_Inv_D);
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/cfe/cfe/arch/mips/cpu/bcmcore/include/
H A Dsbmips.h609 #define Index_Writeback_Inv_D 0x1 /* 0 1 */ macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/cfe/cfe/arch/mips/cpu/rm5200/include/
H A Dr5kc0.h236 #define Index_Writeback_Inv_D 0x1 /* 0 1 */ macro
H A Dsbmips.h607 #define Index_Writeback_Inv_D 0x1 /* 0 1 */ macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/cfe/cfe/arch/mips/cpu/rm7000/include/
H A Dr5kc0.h236 #define Index_Writeback_Inv_D 0x1 /* 0 1 */ macro
H A Dsbmips.h607 #define Index_Writeback_Inv_D 0x1 /* 0 1 */ macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/cfe/cfe/arch/mips/cpu/sb1250/include/
H A Dsbmips.h974 #define Index_Writeback_Inv_D 0x1 /* 0 1 */ macro

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