Searched refs:Imm_None (Results 1 - 3 of 3) sorted by relevance
| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src/router/gdb/include/opcode/ |
| H A D | tic30.h | 239 #define Imm_None 0 macro
250 { "addc3" ,3,0x20000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None },
252 { "addf3" ,3,0x20800000,AddressMode, { TAddr1, TAddr2, Rn }, Imm_None },
254 { "addi3" ,3,0x21000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None },
256 { "and3" ,3,0x21800000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None },
258 { "andn3" ,3,0x22000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None },
260 { "ash3" ,3,0x22800000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None },
261 { "b" ,1,0x68000000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
262 { "bu" ,1,0x68000000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
263 { "blo" ,1,0x68010000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
[all...] |
| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt/router/gdb/include/opcode/ |
| H A D | tic30.h | 239 #define Imm_None 0 macro
250 { "addc3" ,3,0x20000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None },
252 { "addf3" ,3,0x20800000,AddressMode, { TAddr1, TAddr2, Rn }, Imm_None },
254 { "addi3" ,3,0x21000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None },
256 { "and3" ,3,0x21800000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None },
258 { "andn3" ,3,0x22000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None },
260 { "ash3" ,3,0x22800000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None },
261 { "b" ,1,0x68000000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
262 { "bu" ,1,0x68000000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
263 { "blo" ,1,0x68010000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
[all...] |
| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/router/gdb/include/opcode/ |
| H A D | tic30.h | 239 #define Imm_None 0 macro
250 { "addc3" ,3,0x20000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None },
252 { "addf3" ,3,0x20800000,AddressMode, { TAddr1, TAddr2, Rn }, Imm_None },
254 { "addi3" ,3,0x21000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None },
256 { "and3" ,3,0x21800000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None },
258 { "andn3" ,3,0x22000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None },
260 { "ash3" ,3,0x22800000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None },
261 { "b" ,1,0x68000000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
262 { "bu" ,1,0x68000000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
263 { "blo" ,1,0x68010000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
[all...] |
Completed in 169 milliseconds