Searched refs:INT_CLK (Results 1 - 4 of 4) sorted by relevance

/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/m68k/include/asm/
H A Dmacints.h140 #define INT_CLK 24576 /* CLK while int_clk =2.456MHz and divide = 100 */ macro
H A Datariints.h98 #define INT_CLK 24576 /* CLK while int_clk =2.456MHz and divide = 100 */ macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/m68k/include/asm/
H A Dmacints.h140 #define INT_CLK 24576 /* CLK while int_clk =2.456MHz and divide = 100 */ macro
H A Datariints.h98 #define INT_CLK 24576 /* CLK while int_clk =2.456MHz and divide = 100 */ macro

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