Searched refs:IFR (Results 1 - 12 of 12) sorted by relevance

/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/macintosh/
H A Dvia-cuda.c50 #define IFR (13*RS) /* Interrupt flag register */ macro
64 /* Bits in IFR and IER */
187 out_8(&via[IFR], 0x7f); /* clear interrupts by writing 1s */
279 out_8(&via[IFR], SR_INT);
288 WAIT_FOR(in_8(&via[IFR]) & SR_INT, "CUDA response to sync (2)");
290 out_8(&via[IFR], SR_INT);
297 WAIT_FOR(in_8(&via[IFR]) & SR_INT, "CUDA response to sync (4)");
299 out_8(&via[IFR], SR_INT);
467 if ((in_8(&via[IFR]) & SR_INT) == 0) {
471 out_8(&via[IFR], SR_IN
[all...]
H A Dvia-maciisi.c39 #define IFR (13*RS) /* Interrupt flag register */ macro
53 /* Bits in IFR and IER */
164 while (!(via[IFR] & SR_INT) && poll_timeout-- > 0)
209 via[IFR] = SR_INT;
373 printk(KERN_DEBUG "maciisi_start called, state=%d, status=%x, ifr=%x\n", maciisi_state, status, via[IFR]);
421 if (via[IFR] & SR_INT) {
448 printk(KERN_DEBUG "state %d status %x ifr %x\n", maciisi_state, status, via[IFR]);
451 if (!(via[IFR] & SR_INT)) {
459 /* via[IFR] = SR_INT; */
506 /* process this now, because the IFR ha
[all...]
H A Dvia-macii.c56 #define IFR (13*RS) /* Interrupt flag register */ macro
69 /* Bits in IFR and IER */
395 if (via[IFR] & SR_INT)
396 via[IFR] = SR_INT;
H A Dvia-pmu68k.c62 #define IFR (13*RS) /* Interrupt flag register */ macro
75 /* Bits in IFR and IER */
558 if (via1[IFR] & SR_INT) {
559 via1[IFR] = SR_INT;
562 if (via1[IFR] & CB1_INT) {
563 via1[IFR] = CB1_INT;
H A Dvia-pmu.c93 #define IFR (13*RS) /* Interrupt flag register */ macro
106 /* Bits in IFR and IER */
345 out_8(&via[IFR], 0x7f); /* clear IFR */
1446 out_8(&via[IFR], SR_INT);
1559 intr = in_8(&via[IFR]) & (SR_INT | CB1_INT);
1569 out_8(&via[IFR], intr);
1772 out_8(&via[IFR], 0x7f); /* clear IFR */
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/macintosh/
H A Dvia-cuda.c50 #define IFR (13*RS) /* Interrupt flag register */ macro
64 /* Bits in IFR and IER */
187 out_8(&via[IFR], 0x7f); /* clear interrupts by writing 1s */
279 out_8(&via[IFR], SR_INT);
288 WAIT_FOR(in_8(&via[IFR]) & SR_INT, "CUDA response to sync (2)");
290 out_8(&via[IFR], SR_INT);
297 WAIT_FOR(in_8(&via[IFR]) & SR_INT, "CUDA response to sync (4)");
299 out_8(&via[IFR], SR_INT);
467 if ((in_8(&via[IFR]) & SR_INT) == 0) {
471 out_8(&via[IFR], SR_IN
[all...]
H A Dvia-maciisi.c39 #define IFR (13*RS) /* Interrupt flag register */ macro
53 /* Bits in IFR and IER */
164 while (!(via[IFR] & SR_INT) && poll_timeout-- > 0)
209 via[IFR] = SR_INT;
373 printk(KERN_DEBUG "maciisi_start called, state=%d, status=%x, ifr=%x\n", maciisi_state, status, via[IFR]);
421 if (via[IFR] & SR_INT) {
448 printk(KERN_DEBUG "state %d status %x ifr %x\n", maciisi_state, status, via[IFR]);
451 if (!(via[IFR] & SR_INT)) {
459 /* via[IFR] = SR_INT; */
506 /* process this now, because the IFR ha
[all...]
H A Dvia-macii.c56 #define IFR (13*RS) /* Interrupt flag register */ macro
69 /* Bits in IFR and IER */
395 if (via[IFR] & SR_INT)
396 via[IFR] = SR_INT;
H A Dvia-pmu68k.c62 #define IFR (13*RS) /* Interrupt flag register */ macro
75 /* Bits in IFR and IER */
558 if (via1[IFR] & SR_INT) {
559 via1[IFR] = SR_INT;
562 if (via1[IFR] & CB1_INT) {
563 via1[IFR] = CB1_INT;
H A Dvia-pmu.c93 #define IFR (13*RS) /* Interrupt flag register */ macro
106 /* Bits in IFR and IER */
345 out_8(&via[IFR], 0x7f); /* clear IFR */
1446 out_8(&via[IFR], SR_INT);
1559 intr = in_8(&via[IFR]) & (SR_INT | CB1_INT);
1569 out_8(&via[IFR], intr);
1772 out_8(&via[IFR], 0x7f); /* clear IFR */
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/powerpc/platforms/powermac/
H A Dtime.c60 #define IFR (13*RS) /* Interrupt flag register */ macro
66 /* Bits in IFR and IER */
290 while ((in_8(&via[IFR]) & T1_INT) == 0)
295 while ((in_8(&via[IFR]) & T1_INT) == 0)
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/powerpc/platforms/powermac/
H A Dtime.c60 #define IFR (13*RS) /* Interrupt flag register */ macro
66 /* Bits in IFR and IER */
290 while ((in_8(&via[IFR]) & T1_INT) == 0)
295 while ((in_8(&via[IFR]) & T1_INT) == 0)

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