Searched refs:HAL_PRIME_CHNL_OFFSET_LOWER (Results 1 - 12 of 12) sorted by relevance

/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/staging/rtl8192e/
H A Dr8192E.h651 #define HAL_PRIME_CHNL_OFFSET_LOWER 1 macro
H A Dr819xE_phy.c3193 }else if(priv->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER)
3268 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER;
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/staging/rtl8192u/
H A Dr8192U.h716 #define HAL_PRIME_CHNL_OFFSET_LOWER 1 macro
H A Dr819xU_phy.c1674 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER;
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/staging/rtl8192u/
H A Dr8192U.h716 #define HAL_PRIME_CHNL_OFFSET_LOWER 1 macro
H A Dr819xU_phy.c1674 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER;
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/staging/rtl8192e/
H A Dr8192E.h651 #define HAL_PRIME_CHNL_OFFSET_LOWER 1 macro
H A Dr819xE_phy.c3193 }else if(priv->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER)
3268 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER;
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/staging/rtl8192su/
H A Dr8192U.h835 #define HAL_PRIME_CHNL_OFFSET_LOWER 1 macro
H A Dr8192S_phy.c2245 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER;
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/staging/rtl8192su/
H A Dr8192U.h835 #define HAL_PRIME_CHNL_OFFSET_LOWER 1 macro
H A Dr8192S_phy.c2245 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER;

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