Searched refs:GPIO_FPGA_CCLK (Results 1 - 3 of 3) sorted by relevance

/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/mips/include/asm/sibyte/
H A Dcarmel.h32 #define GPIO_FPGA_CCLK 10 macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/mips/include/asm/sibyte/
H A Dcarmel.h32 #define GPIO_FPGA_CCLK 10 macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/cfe/cfe/arch/mips/board/carmel/include/
H A Dcarmel.h108 #define GPIO_FPGA_CCLK 10 /* output */ macro
128 #define M_GPIO_FPGA_CCLK _SB_MAKEMASK1(GPIO_FPGA_CCLK)

Completed in 128 milliseconds