Searched refs:GIC_CPU_INT1 (Results 1 - 8 of 8) sorted by relevance

/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/mips/include/asm/mips-boards/
H A Dsead3int.h36 #define GIC_CPU_INT1 1 /* . */ macro
H A Dmaltaint.h83 #define GIC_CPU_INT1 1 /* . */ macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/mips/include/asm/mips-boards/
H A Dsead3int.h36 #define GIC_CPU_INT1 1 /* . */ macro
H A Dmaltaint.h83 #define GIC_CPU_INT1 1 /* . */ macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/mips/mti-sead3/
H A Dsead3-int.c59 { 0, GIC_CPU_INT1, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/mips/mti-sead3/
H A Dsead3-int.c59 { 0, GIC_CPU_INT1, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/mips/mti-malta/
H A Dmalta-int.c394 { 0, GIC_CPU_INT1, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
465 fill_ipi_map1(gic_resched_int_base, cpu, GIC_CPU_INT1);
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/mips/mti-malta/
H A Dmalta-int.c394 { 0, GIC_CPU_INT1, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
465 fill_ipi_map1(gic_resched_int_base, cpu, GIC_CPU_INT1);

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