Searched refs:FXM (Results 1 - 5 of 5) sorted by relevance
| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/powerpc/xmon/ |
| H A D | ppc-opc.c | 299 /* The FXM field in an XFX instruction. */
300 #define FXM FRS + 1
305 #define FXM4 FXM + 1
1039 /* FXM mask in mfcr and mtcrf instructions. */
1065 /* If only one bit of the FXM field is set, we can use the new form
1795 /* A mask for the FXM version of an XFX form instruction. */
1798 /* An XFX form instruction with the FXM field filled in. */
3393 { "mfocrf", XFXM(31,19,0,1), XFXFXM_MASK, COM, { RT, FXM } },
3552 { "mtocrf", XFXM(31,144,0,1), XFXFXM_MASK, COM, { FXM, RS } },
3554 { "mtcrf", X(31,144), XFXFXM_MASK, COM, { FXM, R
298 #define FXM macro
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| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/powerpc/xmon/ |
| H A D | ppc-opc.c | 299 /* The FXM field in an XFX instruction. */
300 #define FXM FRS + 1
305 #define FXM4 FXM + 1
1039 /* FXM mask in mfcr and mtcrf instructions. */
1065 /* If only one bit of the FXM field is set, we can use the new form
1795 /* A mask for the FXM version of an XFX form instruction. */
1798 /* An XFX form instruction with the FXM field filled in. */
3393 { "mfocrf", XFXM(31,19,0,1), XFXFXM_MASK, COM, { RT, FXM } },
3552 { "mtocrf", XFXM(31,144,0,1), XFXFXM_MASK, COM, { FXM, RS } },
3554 { "mtcrf", X(31,144), XFXFXM_MASK, COM, { FXM, R
298 #define FXM macro
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| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt/router/gdb/opcodes/ |
| H A D | ppc-opc.c | 283 /* The FXM field in an XFX instruction. */
284 #define FXM FRS + 1
288 #define FXM4 FXM + 1
851 /* FXM mask in mfcr and mtcrf instructions. */
877 /* If only one bit of the FXM field is set, we can use the new form
1554 /* A mask for the FXM version of an XFX form instruction. */
1557 /* An XFX form instruction with the FXM field filled in. */
3218 { "mfocrf", XFXM(31,19,0,1), XFXFXM_MASK, COM, { RT, FXM } },
3377 { "mtocrf", XFXM(31,144,0,1), XFXFXM_MASK, COM, { FXM, RS } },
3379 { "mtcrf", X(31,144), XFXFXM_MASK, COM, { FXM, R
282 #define FXM macro
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| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src/router/gdb/opcodes/ |
| H A D | ppc-opc.c | 283 /* The FXM field in an XFX instruction. */
284 #define FXM FRS + 1
288 #define FXM4 FXM + 1
851 /* FXM mask in mfcr and mtcrf instructions. */
877 /* If only one bit of the FXM field is set, we can use the new form
1554 /* A mask for the FXM version of an XFX form instruction. */
1557 /* An XFX form instruction with the FXM field filled in. */
3218 { "mfocrf", XFXM(31,19,0,1), XFXFXM_MASK, COM, { RT, FXM } },
3377 { "mtocrf", XFXM(31,144,0,1), XFXFXM_MASK, COM, { FXM, RS } },
3379 { "mtcrf", X(31,144), XFXFXM_MASK, COM, { FXM, R
282 #define FXM macro
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| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/router/gdb/opcodes/ |
| H A D | ppc-opc.c | 283 /* The FXM field in an XFX instruction. */
284 #define FXM FRS + 1
288 #define FXM4 FXM + 1
851 /* FXM mask in mfcr and mtcrf instructions. */
877 /* If only one bit of the FXM field is set, we can use the new form
1554 /* A mask for the FXM version of an XFX form instruction. */
1557 /* An XFX form instruction with the FXM field filled in. */
3218 { "mfocrf", XFXM(31,19,0,1), XFXFXM_MASK, COM, { RT, FXM } },
3377 { "mtocrf", XFXM(31,144,0,1), XFXFXM_MASK, COM, { FXM, RS } },
3379 { "mtcrf", X(31,144), XFXFXM_MASK, COM, { FXM, R
282 #define FXM macro
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