Searched refs:FShft (Results 1 - 12 of 12) sorted by relevance

/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/video/mbx/
H A Dreg_bits.h8 #define FShft(Field) ((Field) & 0x0000FFFF) macro
9 #define FMsk(Field) (((UData (1) << FSize (Field)) - 1) << FShft (Field))
11 #define F1stBit(Field) (UData (1) << FShft (Field))
17 #define SYSCLKSRC_REF ((0x0) << FShft(SYSCLKSRC_SEL))
18 #define SYSCLKSRC_PLL_1 ((0x1) << FShft(SYSCLKSRC_SEL))
19 #define SYSCLKSRC_PLL_2 ((0x2) << FShft(SYSCLKSRC_SEL))
23 #define PIXCLKSRC_REF ((0x0) << FShft(PIXCLKSRC_SEL))
24 #define PIXCLKSRC_PLL_1 ((0x1) << FShft(PIXCLKSRC_SEL))
25 #define PIXCLKSRC_PLL_2 ((0x2) << FShft(PIXCLKSRC_SEL))
32 #define Core_Pll_M(x) ((x) << FShft(CORE_PLL_
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/video/mbx/
H A Dreg_bits.h8 #define FShft(Field) ((Field) & 0x0000FFFF) macro
9 #define FMsk(Field) (((UData (1) << FSize (Field)) - 1) << FShft (Field))
11 #define F1stBit(Field) (UData (1) << FShft (Field))
17 #define SYSCLKSRC_REF ((0x0) << FShft(SYSCLKSRC_SEL))
18 #define SYSCLKSRC_PLL_1 ((0x1) << FShft(SYSCLKSRC_SEL))
19 #define SYSCLKSRC_PLL_2 ((0x2) << FShft(SYSCLKSRC_SEL))
23 #define PIXCLKSRC_REF ((0x0) << FShft(PIXCLKSRC_SEL))
24 #define PIXCLKSRC_PLL_1 ((0x1) << FShft(PIXCLKSRC_SEL))
25 #define PIXCLKSRC_PLL_2 ((0x2) << FShft(PIXCLKSRC_SEL))
32 #define Core_Pll_M(x) ((x) << FShft(CORE_PLL_
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mach-pxa/include/mach/
H A Dbitfield.h50 * MACROS: FSize, FShft, FMsk, FAlnMsk, F1stBit
53 * The macros "FSize", "FShft", "FMsk", "FAlnMsk", and "F1stBit" return
62 * FShft Shift value of the bit field with respect to bit 0.
69 #define FShft(Field) ((Field) & 0x0000FFFF) macro
70 #define FMsk(Field) (((UData (1) << FSize (Field)) - 1) << FShft (Field))
72 #define F1stBit(Field) (UData (1) << FShft (Field))
91 (UData (Value) << FShft (Field))
110 ((UData (Data) >> FShft (Field)) & FAlnMsk (Field))
H A Dregs-lcd.h89 #define LCCR1_DisWdth(Pixel) (((Pixel) - 1) << FShft (LCCR1_PPL))
92 #define LCCR1_HorSnchWdth(Tpix) (((Tpix) - 1) << FShft (LCCR1_HSW))
95 #define LCCR1_EndLnDel(Tpix) (((Tpix) - 1) << FShft (LCCR1_ELW))
98 #define LCCR1_BegLnDel(Tpix) (((Tpix) - 1) << FShft (LCCR1_BLW))
101 #define LCCR2_DisHght(Line) (((Line) - 1) << FShft (LCCR2_LPP))
104 #define LCCR2_VrtSnchWdth(Tln) (((Tln) - 1) << FShft (LCCR2_VSW))
107 #define LCCR2_EndFrmDel(Tln) ((Tln) << FShft (LCCR2_EFW))
110 #define LCCR2_BegFrmDel(Tln) ((Tln) << FShft (LCCR2_BFW))
126 #define LCCR3_PixClkDiv(Div) (((Div) << FShft (LCCR3_PCD)))
129 #define LCCR3_Acb(Acb) (((Acb) << FShft (LCCR3_AC
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mach-sa1100/include/mach/
H A Dbitfield.h50 * MACROS: FSize, FShft, FMsk, FAlnMsk, F1stBit
53 * The macros "FSize", "FShft", "FMsk", "FAlnMsk", and "F1stBit" return
62 * FShft Shift value of the bit field with respect to bit 0.
69 #define FShft(Field) ((Field) & 0x0000FFFF) macro
70 #define FMsk(Field) (((UData (1) << FSize (Field)) - 1) << FShft (Field))
72 #define F1stBit(Field) (UData (1) << FShft (Field))
91 (UData (Value) << FShft (Field))
110 ((UData (Data) >> FShft (Field)) & FAlnMsk (Field))
H A DSA-1100.h142 (((Size) - 1) << FShft (UDCOMP_OUTMAXP))
148 (((Size) - 1) << FShft (UDCIMP_INMAXP))
342 FShft (UTCR1_BRD))
345 FShft (UTCR2_BRD))
350 FShft (UTCR1_BRD))
353 FShft (UTCR2_BRD))
476 FShft (SDCR3_BRD))
479 FShft (SDCR4_BRD))
484 FShft (SDCR3_BRD))
487 FShft (SDCR4_BR
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H A DSA-1101.h107 (( (x) - 8 ) << FShft (SMCR_DCAC))
109 (( (x) - 9 ) << FShft (SMCR_DRAC))
118 ( (x) << FShft (SNPR_VFBsize))
120 (( (x) + 1 ) << FShft (SNPR_BankSelect ))
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-sa1100/include/mach/
H A Dbitfield.h50 * MACROS: FSize, FShft, FMsk, FAlnMsk, F1stBit
53 * The macros "FSize", "FShft", "FMsk", "FAlnMsk", and "F1stBit" return
62 * FShft Shift value of the bit field with respect to bit 0.
69 #define FShft(Field) ((Field) & 0x0000FFFF) macro
70 #define FMsk(Field) (((UData (1) << FSize (Field)) - 1) << FShft (Field))
72 #define F1stBit(Field) (UData (1) << FShft (Field))
91 (UData (Value) << FShft (Field))
110 ((UData (Data) >> FShft (Field)) & FAlnMsk (Field))
H A DSA-1100.h142 (((Size) - 1) << FShft (UDCOMP_OUTMAXP))
148 (((Size) - 1) << FShft (UDCIMP_INMAXP))
342 FShft (UTCR1_BRD))
345 FShft (UTCR2_BRD))
350 FShft (UTCR1_BRD))
353 FShft (UTCR2_BRD))
476 FShft (SDCR3_BRD))
479 FShft (SDCR4_BRD))
484 FShft (SDCR3_BRD))
487 FShft (SDCR4_BR
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H A DSA-1101.h107 (( (x) - 8 ) << FShft (SMCR_DCAC))
109 (( (x) - 9 ) << FShft (SMCR_DRAC))
118 ( (x) << FShft (SNPR_VFBsize))
120 (( (x) + 1 ) << FShft (SNPR_BankSelect ))
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-pxa/include/mach/
H A Dbitfield.h50 * MACROS: FSize, FShft, FMsk, FAlnMsk, F1stBit
53 * The macros "FSize", "FShft", "FMsk", "FAlnMsk", and "F1stBit" return
62 * FShft Shift value of the bit field with respect to bit 0.
69 #define FShft(Field) ((Field) & 0x0000FFFF) macro
70 #define FMsk(Field) (((UData (1) << FSize (Field)) - 1) << FShft (Field))
72 #define F1stBit(Field) (UData (1) << FShft (Field))
91 (UData (Value) << FShft (Field))
110 ((UData (Data) >> FShft (Field)) & FAlnMsk (Field))
H A Dregs-lcd.h89 #define LCCR1_DisWdth(Pixel) (((Pixel) - 1) << FShft (LCCR1_PPL))
92 #define LCCR1_HorSnchWdth(Tpix) (((Tpix) - 1) << FShft (LCCR1_HSW))
95 #define LCCR1_EndLnDel(Tpix) (((Tpix) - 1) << FShft (LCCR1_ELW))
98 #define LCCR1_BegLnDel(Tpix) (((Tpix) - 1) << FShft (LCCR1_BLW))
101 #define LCCR2_DisHght(Line) (((Line) - 1) << FShft (LCCR2_LPP))
104 #define LCCR2_VrtSnchWdth(Tln) (((Tln) - 1) << FShft (LCCR2_VSW))
107 #define LCCR2_EndFrmDel(Tln) ((Tln) << FShft (LCCR2_EFW))
110 #define LCCR2_BegFrmDel(Tln) ((Tln) << FShft (LCCR2_BFW))
126 #define LCCR3_PixClkDiv(Div) (((Div) << FShft (LCCR3_PCD)))
129 #define LCCR3_Acb(Acb) (((Acb) << FShft (LCCR3_AC
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