Searched refs:EMAC_MMC_TIRQS (Results 1 - 12 of 12) sorted by relevance

/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/blackfin/mach-bf518/include/mach/
H A DcdefBF516.h80 #define bfin_read_EMAC_MMC_TIRQS() bfin_read32(EMAC_MMC_TIRQS)
81 #define bfin_write_EMAC_MMC_TIRQS(val) bfin_write32(EMAC_MMC_TIRQS, val)
H A DdefBF516.h48 #define EMAC_MMC_TIRQS 0xFFC0308C /* MMC TX Interrupt Status Register */ macro
366 /* EMAC_MMC_TIRQS and EMAC_MMC_TIRQE Masks */
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/blackfin/mach-bf527/include/mach/
H A DcdefBF527.h80 #define bfin_read_EMAC_MMC_TIRQS() bfin_read32(EMAC_MMC_TIRQS)
81 #define bfin_write_EMAC_MMC_TIRQS(val) bfin_write32(EMAC_MMC_TIRQS, val)
H A DdefBF527.h47 #define EMAC_MMC_TIRQS 0xFFC0308C /* MMC TX Interrupt Status Register */ macro
365 /* EMAC_MMC_TIRQS and EMAC_MMC_TIRQE Masks */
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/blackfin/mach-bf537/include/mach/
H A DcdefBF537.h80 #define bfin_read_EMAC_MMC_TIRQS() bfin_read32(EMAC_MMC_TIRQS)
81 #define bfin_write_EMAC_MMC_TIRQS(val) bfin_write32(EMAC_MMC_TIRQS,val)
H A DdefBF537.h53 #define EMAC_MMC_TIRQS 0xFFC0308C /* MMC TX Interrupt Status Register */ macro
355 /* EMAC_MMC_TIRQS and EMAC_MMC_TIRQE Masks */
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/blackfin/mach-bf518/include/mach/
H A DcdefBF516.h80 #define bfin_read_EMAC_MMC_TIRQS() bfin_read32(EMAC_MMC_TIRQS)
81 #define bfin_write_EMAC_MMC_TIRQS(val) bfin_write32(EMAC_MMC_TIRQS, val)
H A DdefBF516.h48 #define EMAC_MMC_TIRQS 0xFFC0308C /* MMC TX Interrupt Status Register */ macro
366 /* EMAC_MMC_TIRQS and EMAC_MMC_TIRQE Masks */
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/blackfin/mach-bf527/include/mach/
H A DcdefBF527.h80 #define bfin_read_EMAC_MMC_TIRQS() bfin_read32(EMAC_MMC_TIRQS)
81 #define bfin_write_EMAC_MMC_TIRQS(val) bfin_write32(EMAC_MMC_TIRQS, val)
H A DdefBF527.h47 #define EMAC_MMC_TIRQS 0xFFC0308C /* MMC TX Interrupt Status Register */ macro
365 /* EMAC_MMC_TIRQS and EMAC_MMC_TIRQE Masks */
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/blackfin/mach-bf537/include/mach/
H A DcdefBF537.h80 #define bfin_read_EMAC_MMC_TIRQS() bfin_read32(EMAC_MMC_TIRQS)
81 #define bfin_write_EMAC_MMC_TIRQS(val) bfin_write32(EMAC_MMC_TIRQS,val)
H A DdefBF537.h53 #define EMAC_MMC_TIRQS 0xFFC0308C /* MMC TX Interrupt Status Register */ macro
355 /* EMAC_MMC_TIRQS and EMAC_MMC_TIRQE Masks */

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