Searched refs:EHEA_BMASK_SET (Results 1 - 8 of 8) sorted by relevance

/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/net/ehea/
H A Dehea_phyp.c220 EHEA_BMASK_SET(H_ALL_RES_QP_EQPO, init_attr->low_lat_rq1 ? 1 : 0)
221 | EHEA_BMASK_SET(H_ALL_RES_QP_QPP, 0)
222 | EHEA_BMASK_SET(H_ALL_RES_QP_RQR, 6) /* rq1 & rq2 & rq3 */
223 | EHEA_BMASK_SET(H_ALL_RES_QP_EQEG, 0) /* EQE gen. disabled */
224 | EHEA_BMASK_SET(H_ALL_RES_QP_LL_QP, init_attr->low_lat_rq1)
225 | EHEA_BMASK_SET(H_ALL_RES_QP_DMA128, 0)
226 | EHEA_BMASK_SET(H_ALL_RES_QP_HSM, 0)
227 | EHEA_BMASK_SET(H_ALL_RES_QP_SIGT, init_attr->signalingtype)
228 | EHEA_BMASK_SET(H_ALL_RES_QP_RES_TYP, H_ALL_RES_TYPE_QP);
230 u64 r9_reg = EHEA_BMASK_SET(H_ALL_RES_QP_P
[all...]
H A Dehea_hw.h247 EHEA_BMASK_SET(QPX_SQA_VALUE, nr_wqes));
254 EHEA_BMASK_SET(QPX_RQ1A_VALUE, nr_wqes));
261 EHEA_BMASK_SET(QPX_RQ2A_VALUE, nr_wqes));
268 EHEA_BMASK_SET(QPX_RQ3A_VALUE, nr_wqes));
275 EHEA_BMASK_SET(CQX_FECADDER, nr_cqes));
282 EHEA_BMASK_SET(CQX_N1_GENERATE_COMP_EVENT, 1));
289 EHEA_BMASK_SET(CQX_EP_EVENT_PENDING, 0));
H A Dehea_main.c477 rwqe->wr_id = EHEA_BMASK_SET(EHEA_WR_ID_TYPE, wqe_type)
478 | EHEA_BMASK_SET(EHEA_WR_ID_INDEX, index);
1036 EHEA_BMASK_SET(H_PORT_CB0_ALL, 0xFFFF),
1292 event_mask = EHEA_BMASK_SET(NELR_PORTSTATE_CHG, 1)
1293 | EHEA_BMASK_SET(NELR_ADAPTER_MALFUNC, 1)
1294 | EHEA_BMASK_SET(NELR_PORT_MALFUNC, 1);
1418 cb0->port_rc = EHEA_BMASK_SET(PXLY_RC_VALID, 1)
1419 | EHEA_BMASK_SET(PXLY_RC_IP_CHKSUM, 1)
1420 | EHEA_BMASK_SET(PXLY_RC_TCP_UDP_CHKSUM, 1)
1421 | EHEA_BMASK_SET(PXLY_RC_VLAN_XTRAC
[all...]
H A Dehea.h157 #define EHEA_BMASK_SET(mask, value) \ macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/net/ehea/
H A Dehea_phyp.c220 EHEA_BMASK_SET(H_ALL_RES_QP_EQPO, init_attr->low_lat_rq1 ? 1 : 0)
221 | EHEA_BMASK_SET(H_ALL_RES_QP_QPP, 0)
222 | EHEA_BMASK_SET(H_ALL_RES_QP_RQR, 6) /* rq1 & rq2 & rq3 */
223 | EHEA_BMASK_SET(H_ALL_RES_QP_EQEG, 0) /* EQE gen. disabled */
224 | EHEA_BMASK_SET(H_ALL_RES_QP_LL_QP, init_attr->low_lat_rq1)
225 | EHEA_BMASK_SET(H_ALL_RES_QP_DMA128, 0)
226 | EHEA_BMASK_SET(H_ALL_RES_QP_HSM, 0)
227 | EHEA_BMASK_SET(H_ALL_RES_QP_SIGT, init_attr->signalingtype)
228 | EHEA_BMASK_SET(H_ALL_RES_QP_RES_TYP, H_ALL_RES_TYPE_QP);
230 u64 r9_reg = EHEA_BMASK_SET(H_ALL_RES_QP_P
[all...]
H A Dehea_hw.h247 EHEA_BMASK_SET(QPX_SQA_VALUE, nr_wqes));
254 EHEA_BMASK_SET(QPX_RQ1A_VALUE, nr_wqes));
261 EHEA_BMASK_SET(QPX_RQ2A_VALUE, nr_wqes));
268 EHEA_BMASK_SET(QPX_RQ3A_VALUE, nr_wqes));
275 EHEA_BMASK_SET(CQX_FECADDER, nr_cqes));
282 EHEA_BMASK_SET(CQX_N1_GENERATE_COMP_EVENT, 1));
289 EHEA_BMASK_SET(CQX_EP_EVENT_PENDING, 0));
H A Dehea_main.c477 rwqe->wr_id = EHEA_BMASK_SET(EHEA_WR_ID_TYPE, wqe_type)
478 | EHEA_BMASK_SET(EHEA_WR_ID_INDEX, index);
1036 EHEA_BMASK_SET(H_PORT_CB0_ALL, 0xFFFF),
1292 event_mask = EHEA_BMASK_SET(NELR_PORTSTATE_CHG, 1)
1293 | EHEA_BMASK_SET(NELR_ADAPTER_MALFUNC, 1)
1294 | EHEA_BMASK_SET(NELR_PORT_MALFUNC, 1);
1418 cb0->port_rc = EHEA_BMASK_SET(PXLY_RC_VALID, 1)
1419 | EHEA_BMASK_SET(PXLY_RC_IP_CHKSUM, 1)
1420 | EHEA_BMASK_SET(PXLY_RC_TCP_UDP_CHKSUM, 1)
1421 | EHEA_BMASK_SET(PXLY_RC_VLAN_XTRAC
[all...]
H A Dehea.h157 #define EHEA_BMASK_SET(mask, value) \ macro

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