Searched refs:DSP_CACHE_LINE (Results 1 - 2 of 2) sorted by relevance

/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/staging/tidspbridge/rmgr/
H A Dproc.c70 #define DSP_CACHE_LINE 128 macro
1344 if (!IS_ALIGNED((u32)pmpu_addr, DSP_CACHE_LINE) ||
1345 !IS_ALIGNED(ul_size, DSP_CACHE_LINE)) {
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/staging/tidspbridge/rmgr/
H A Dproc.c70 #define DSP_CACHE_LINE 128 macro
1344 if (!IS_ALIGNED((u32)pmpu_addr, DSP_CACHE_LINE) ||
1345 !IS_ALIGNED(ul_size, DSP_CACHE_LINE)) {

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