Searched refs:DPLL_CTL (Results 1 - 8 of 8) sorted by relevance
| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/plat-omap/include/plat/ |
| H A D | system.h | 28 omap_writew(omap_readw(DPLL_CTL) & ~(1 << 4),
29 DPLL_CTL);
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| H A D | hardware.h | 89 #define DPLL_CTL (0xfffecf00) macro
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| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/plat-omap/include/plat/ |
| H A D | system.h | 28 omap_writew(omap_readw(DPLL_CTL) & ~(1 << 4),
29 DPLL_CTL);
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| H A D | hardware.h | 89 #define DPLL_CTL (0xfffecf00) macro
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| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mach-omap1/ |
| H A D | sram.S | 24 mov r2, #OMAP1_IO_ADDRESS(DPLL_CTL) & 0xff000000
25 orr r2, r2, #OMAP1_IO_ADDRESS(DPLL_CTL) & 0x00ff0000
26 orr r2, r2, #OMAP1_IO_ADDRESS(DPLL_CTL) & 0x0000ff00
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| H A D | clock_data.c | 787 pr_info("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: "
788 "0x%04x\n", omap_readw(ARM_SYSST), omap_readw(DPLL_CTL),
799 unsigned pll_ctl_val = omap_readw(DPLL_CTL);
826 omap_writew(0x2290, DPLL_CTL);
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| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-omap1/ |
| H A D | sram.S | 24 mov r2, #OMAP1_IO_ADDRESS(DPLL_CTL) & 0xff000000
25 orr r2, r2, #OMAP1_IO_ADDRESS(DPLL_CTL) & 0x00ff0000
26 orr r2, r2, #OMAP1_IO_ADDRESS(DPLL_CTL) & 0x0000ff00
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| H A D | clock_data.c | 787 pr_info("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: "
788 "0x%04x\n", omap_readw(ARM_SYSST), omap_readw(DPLL_CTL),
799 unsigned pll_ctl_val = omap_readw(DPLL_CTL);
826 omap_writew(0x2290, DPLL_CTL);
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