Searched refs:DIV4_NR (Results 1 - 20 of 20) sorted by relevance

/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/sh/kernel/cpu/sh4a/
H A Dclock-sh7722.c120 enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, DIV4_NR }; enumerator in enum:__anon25787
122 struct clk div4_clks[DIV4_NR] = {
271 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
H A Dclock-sh7366.c118 DIV4_SIUA, DIV4_SIUB, DIV4_NR }; enumerator in enum:__anon25784
123 struct clk div4_clks[DIV4_NR] = {
286 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
H A Dclock-sh7785.c67 DIV4_DU, DIV4_P, DIV4_NR }; enumerator in enum:__anon25797
72 struct clk div4_clks[DIV4_NR] = {
H A Dclock-sh7786.c68 enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_DDR, DIV4_DU, DIV4_P, DIV4_NR }; enumerator in enum:__anon25799
73 struct clk div4_clks[DIV4_NR] = {
H A Dclock-sh7343.c115 DIV4_SIUA, DIV4_SIUB, DIV4_NR }; enumerator in enum:__anon25781
120 struct clk div4_clks[DIV4_NR] = {
297 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
H A Dclock-sh7723.c118 enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, DIV4_NR }; enumerator in enum:__anon25791
123 struct clk div4_clks[DIV4_NR] = {
347 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
H A Dclock-sh7724.c144 enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_P, DIV4_M1, DIV4_NR }; enumerator in enum:__anon25795
149 struct clk div4_clks[DIV4_NR] = {
373 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/sh/kernel/cpu/sh4a/
H A Dclock-sh7722.c120 enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, DIV4_NR }; enumerator in enum:__anon14094
122 struct clk div4_clks[DIV4_NR] = {
271 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
H A Dclock-sh7366.c118 DIV4_SIUA, DIV4_SIUB, DIV4_NR }; enumerator in enum:__anon14091
123 struct clk div4_clks[DIV4_NR] = {
286 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
H A Dclock-sh7785.c67 DIV4_DU, DIV4_P, DIV4_NR }; enumerator in enum:__anon14104
72 struct clk div4_clks[DIV4_NR] = {
H A Dclock-sh7786.c68 enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_DDR, DIV4_DU, DIV4_P, DIV4_NR }; enumerator in enum:__anon14106
73 struct clk div4_clks[DIV4_NR] = {
H A Dclock-sh7343.c115 DIV4_SIUA, DIV4_SIUB, DIV4_NR }; enumerator in enum:__anon14088
120 struct clk div4_clks[DIV4_NR] = {
297 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
H A Dclock-sh7723.c118 enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, DIV4_NR }; enumerator in enum:__anon14098
123 struct clk div4_clks[DIV4_NR] = {
347 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
H A Dclock-sh7724.c144 enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_P, DIV4_M1, DIV4_NR }; enumerator in enum:__anon14102
149 struct clk div4_clks[DIV4_NR] = {
373 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mach-shmobile/
H A Dclock-sh7367.c177 DIV4_ZS, DIV4_ZB, DIV4_ZB3, DIV4_CP, DIV4_NR }; enumerator in enum:__anon11869
182 static struct clk div4_clks[DIV4_NR] = {
344 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
H A Dclock-sh7377.c187 DIV4_ZS, DIV4_ZB, DIV4_ZB3, DIV4_CP, DIV4_NR }; enumerator in enum:__anon11876
192 static struct clk div4_clks[DIV4_NR] = {
355 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
H A Dclock-sh7372.c336 DIV4_DDRP, DIV4_NR }; enumerator in enum:__anon11872
341 static struct clk div4_clks[DIV4_NR] = {
545 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-shmobile/
H A Dclock-sh7367.c177 DIV4_ZS, DIV4_ZB, DIV4_ZB3, DIV4_CP, DIV4_NR }; enumerator in enum:__anon23562
182 static struct clk div4_clks[DIV4_NR] = {
344 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
H A Dclock-sh7377.c187 DIV4_ZS, DIV4_ZB, DIV4_ZB3, DIV4_CP, DIV4_NR }; enumerator in enum:__anon23569
192 static struct clk div4_clks[DIV4_NR] = {
355 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
H A Dclock-sh7372.c336 DIV4_DDRP, DIV4_NR }; enumerator in enum:__anon23565
341 static struct clk div4_clks[DIV4_NR] = {
545 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);

Completed in 84 milliseconds