Searched refs:DAVINCI_MCASP_ACLKXCTL_REG (Results 1 - 2 of 2) sorted by relevance
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/sound/soc/davinci/ |
H A D | davinci-mcasp.c | 77 #define DAVINCI_MCASP_ACLKXCTL_REG 0xb0 macro 189 * DAVINCI_MCASP_ACLKXCTL_REG - Transmit Clock Control Register Bits 431 mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); 441 mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); 451 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); 466 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); 474 mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); 482 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); 490 mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); 637 mcasp_clr_bits(dev->base + DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYN [all...] |
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/sound/soc/davinci/ |
H A D | davinci-mcasp.c | 77 #define DAVINCI_MCASP_ACLKXCTL_REG 0xb0 macro 189 * DAVINCI_MCASP_ACLKXCTL_REG - Transmit Clock Control Register Bits 431 mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); 441 mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); 451 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); 466 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); 474 mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); 482 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); 490 mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); 637 mcasp_clr_bits(dev->base + DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYN [all...] |
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