Searched refs:CACHE_WAY_SIZE (Results 1 - 4 of 4) sorted by relevance

/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/xtensa/include/asm/
H A Dcache.h27 # define CACHE_WAY_SIZE DCACHE_WAY_SIZE macro
29 # define CACHE_WAY_SIZE ICACHE_WAY_SIZE macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/xtensa/include/asm/
H A Dcache.h27 # define CACHE_WAY_SIZE DCACHE_WAY_SIZE macro
29 # define CACHE_WAY_SIZE ICACHE_WAY_SIZE macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mm/
H A Dcache-xsc3l2.c35 #define CACHE_WAY_SIZE(l2ctype) (8192 << (((l2ctype) >> 8) & 0xf)) macro
36 #define CACHE_SET_SIZE(l2ctype) (CACHE_WAY_SIZE(l2ctype) >> CACHE_LINE_SHIFT)
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mm/
H A Dcache-xsc3l2.c35 #define CACHE_WAY_SIZE(l2ctype) (8192 << (((l2ctype) >> 8) & 0xf)) macro
36 #define CACHE_SET_SIZE(l2ctype) (CACHE_WAY_SIZE(l2ctype) >> CACHE_LINE_SHIFT)

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