Searched refs:CACHELINESIZE (Results 1 - 6 of 6) sorted by relevance

/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mm/
H A Dproc-xsc3.S47 #define CACHELINESIZE 32 define
188 add r0, r0, #CACHELINESIZE
213 bic r0, r0, #CACHELINESIZE - 1
215 add r0, r0, #CACHELINESIZE
236 add r0, r0, #CACHELINESIZE
257 tst r0, #CACHELINESIZE - 1
258 bic r0, r0, #CACHELINESIZE - 1
260 tst r1, #CACHELINESIZE - 1
263 add r0, r0, #CACHELINESIZE
278 bic r0, r0, #CACHELINESIZE
[all...]
H A Dproc-xscale.S42 #define CACHELINESIZE 32 define
95 add \rd, \rd, #CACHELINESIZE
97 add \rd, \rd, #CACHELINESIZE
99 add \rd, \rd, #CACHELINESIZE
101 add \rd, \rd, #CACHELINESIZE
228 add r0, r0, #CACHELINESIZE
250 bic r0, r0, #CACHELINESIZE - 1
252 add r0, r0, #CACHELINESIZE
271 bic r0, r0, #CACHELINESIZE - 1
274 add r0, r0, #CACHELINESIZE
[all...]
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mm/
H A Dproc-xsc3.S47 #define CACHELINESIZE 32 define
188 add r0, r0, #CACHELINESIZE
213 bic r0, r0, #CACHELINESIZE - 1
215 add r0, r0, #CACHELINESIZE
236 add r0, r0, #CACHELINESIZE
257 tst r0, #CACHELINESIZE - 1
258 bic r0, r0, #CACHELINESIZE - 1
260 tst r1, #CACHELINESIZE - 1
263 add r0, r0, #CACHELINESIZE
278 bic r0, r0, #CACHELINESIZE
[all...]
H A Dproc-xscale.S42 #define CACHELINESIZE 32 define
95 add \rd, \rd, #CACHELINESIZE
97 add \rd, \rd, #CACHELINESIZE
99 add \rd, \rd, #CACHELINESIZE
101 add \rd, \rd, #CACHELINESIZE
228 add r0, r0, #CACHELINESIZE
250 bic r0, r0, #CACHELINESIZE - 1
252 add r0, r0, #CACHELINESIZE
271 bic r0, r0, #CACHELINESIZE - 1
274 add r0, r0, #CACHELINESIZE
[all...]
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/mtd/maps/
H A Dpxa2xx-flash.c27 #define CACHELINESIZE 32 macro
35 start &= ~(CACHELINESIZE - 1);
39 start += CACHELINESIZE;
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/mtd/maps/
H A Dpxa2xx-flash.c27 #define CACHELINESIZE 32 macro
35 start &= ~(CACHELINESIZE - 1);
39 start += CACHELINESIZE;

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