Searched refs:CA91CX42_LSI_CTL (Results 1 - 4 of 4) sorted by relevance

/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/staging/vme/bridges/
H A Dvme_ca91cx42.c647 temp_ctl = ioread32(bridge->base + CA91CX42_LSI_CTL[i]);
649 iowrite32(temp_ctl, bridge->base + CA91CX42_LSI_CTL[i]);
725 iowrite32(temp_ctl, bridge->base + CA91CX42_LSI_CTL[i]);
730 iowrite32(temp_ctl, bridge->base + CA91CX42_LSI_CTL[i]);
755 ctl = ioread32(bridge->base + CA91CX42_LSI_CTL[i]);
H A Dvme_ca91cx42.h122 static const int CA91CX42_LSI_CTL[] = { LSI0_CTL, LSI1_CTL, LSI2_CTL, LSI3_CTL, variable
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/staging/vme/bridges/
H A Dvme_ca91cx42.c647 temp_ctl = ioread32(bridge->base + CA91CX42_LSI_CTL[i]);
649 iowrite32(temp_ctl, bridge->base + CA91CX42_LSI_CTL[i]);
725 iowrite32(temp_ctl, bridge->base + CA91CX42_LSI_CTL[i]);
730 iowrite32(temp_ctl, bridge->base + CA91CX42_LSI_CTL[i]);
755 ctl = ioread32(bridge->base + CA91CX42_LSI_CTL[i]);
H A Dvme_ca91cx42.h122 static const int CA91CX42_LSI_CTL[] = { LSI0_CTL, LSI1_CTL, LSI2_CTL, LSI3_CTL, variable

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