/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/gpu/drm/nouveau/ |
H A D | nv50_fbcon.c | 28 BEGIN_RING(chan, NvSub2D, 0x02ac, 1); 31 BEGIN_RING(chan, NvSub2D, 0x0588, 1); 37 BEGIN_RING(chan, NvSub2D, 0x0600, 4); 43 BEGIN_RING(chan, NvSub2D, 0x02ac, 1); 69 BEGIN_RING(chan, NvSub2D, 0x0110, 1); 71 BEGIN_RING(chan, NvSub2D, 0x08b0, 4); 76 BEGIN_RING(chan, NvSub2D, 0x08d0, 4); 115 BEGIN_RING(chan, NvSub2D, 0x0814, 2); 124 BEGIN_RING(chan, NvSub2D, 0x0838, 2); 127 BEGIN_RING(cha [all...] |
H A D | nv04_fbcon.c | 50 BEGIN_RING(chan, NvSubImageBlit, 0x0300, 3); 77 BEGIN_RING(chan, NvSubGdiRect, 0x02fc, 1); 79 BEGIN_RING(chan, NvSubGdiRect, 0x03fc, 1); 85 BEGIN_RING(chan, NvSubGdiRect, 0x0400, 2); 133 BEGIN_RING(chan, NvSubGdiRect, 0x0be4, 7); 152 BEGIN_RING(chan, NvSubGdiRect, 0x0c00, iter_len); 249 BEGIN_RING(chan, sub, 0x0000, 1); 251 BEGIN_RING(chan, sub, 0x0184, 2); 254 BEGIN_RING(chan, sub, 0x0300, 4); 260 BEGIN_RING(cha [all...] |
H A D | nv50_cursor.c | 56 BEGIN_RING(evo, 0, NV84_EVO_CRTC(nv_crtc->index, CURSOR_DMA), 1); 59 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, CURSOR_CTRL), 2); 64 BEGIN_RING(evo, 0, NV50_EVO_UPDATE, 1); 89 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, CURSOR_CTRL), 2); 93 BEGIN_RING(evo, 0, NV84_EVO_CRTC(nv_crtc->index, CURSOR_DMA), 1); 98 BEGIN_RING(evo, 0, NV50_EVO_UPDATE, 1);
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H A D | nv50_crtc.c | 82 BEGIN_RING(evo, 0, NV50_EVO_CRTC(index, CLUT_MODE), 2); 86 BEGIN_RING(evo, 0, NV84_EVO_CRTC(index, CLUT_DMA), 1); 90 BEGIN_RING(evo, 0, NV50_EVO_CRTC(index, FB_DMA), 1); 103 BEGIN_RING(evo, 0, NV50_EVO_CRTC(index, CLUT_MODE), 2); 110 BEGIN_RING(evo, 0, NV84_EVO_CRTC(index, CLUT_DMA), 1); 114 BEGIN_RING(evo, 0, NV50_EVO_CRTC(index, FB_OFFSET), 2); 117 BEGIN_RING(evo, 0, NV50_EVO_CRTC(index, FB_DMA), 1); 150 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, DITHER_CTRL), 1); 157 BEGIN_RING(evo, 0, NV50_EVO_UPDATE, 1); 242 BEGIN_RING(ev [all...] |
H A D | nv50_dac.c | 59 BEGIN_RING(evo, 0, NV50_EVO_DAC(nv_encoder->or, MODE_CTRL), 1); 61 BEGIN_RING(evo, 0, NV50_EVO_UPDATE, 1); 253 BEGIN_RING(evo, 0, NV50_EVO_DAC(nv_encoder->or, MODE_CTRL), 2);
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H A D | nouveau_dma.c | 111 BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_NAME, 1); 113 BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_DMA_NOTIFY, 1); 120 BEGIN_RING(chan, NvSubSw, 0, 1);
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H A D | nv50_sor.c | 59 BEGIN_RING(evo, 0, NV50_EVO_SOR(nv_encoder->or, MODE_CTRL), 1); 61 BEGIN_RING(evo, 0, NV50_EVO_UPDATE, 1); 237 BEGIN_RING(evo, 0, NV50_EVO_SOR(nv_encoder->or, MODE_CTRL), 1);
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H A D | nouveau_dma.h | 127 BEGIN_RING(struct nouveau_channel *chan, int subc, int mthd, int size) function
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H A D | nouveau_fence.c | 146 BEGIN_RING(chan, NvSubSw, USE_REFCNT ? 0x0050 : 0x0150, 1);
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/gpu/drm/nouveau/ |
H A D | nv50_fbcon.c | 28 BEGIN_RING(chan, NvSub2D, 0x02ac, 1); 31 BEGIN_RING(chan, NvSub2D, 0x0588, 1); 37 BEGIN_RING(chan, NvSub2D, 0x0600, 4); 43 BEGIN_RING(chan, NvSub2D, 0x02ac, 1); 69 BEGIN_RING(chan, NvSub2D, 0x0110, 1); 71 BEGIN_RING(chan, NvSub2D, 0x08b0, 4); 76 BEGIN_RING(chan, NvSub2D, 0x08d0, 4); 115 BEGIN_RING(chan, NvSub2D, 0x0814, 2); 124 BEGIN_RING(chan, NvSub2D, 0x0838, 2); 127 BEGIN_RING(cha [all...] |
H A D | nv04_fbcon.c | 50 BEGIN_RING(chan, NvSubImageBlit, 0x0300, 3); 77 BEGIN_RING(chan, NvSubGdiRect, 0x02fc, 1); 79 BEGIN_RING(chan, NvSubGdiRect, 0x03fc, 1); 85 BEGIN_RING(chan, NvSubGdiRect, 0x0400, 2); 133 BEGIN_RING(chan, NvSubGdiRect, 0x0be4, 7); 152 BEGIN_RING(chan, NvSubGdiRect, 0x0c00, iter_len); 249 BEGIN_RING(chan, sub, 0x0000, 1); 251 BEGIN_RING(chan, sub, 0x0184, 2); 254 BEGIN_RING(chan, sub, 0x0300, 4); 260 BEGIN_RING(cha [all...] |
H A D | nv50_cursor.c | 56 BEGIN_RING(evo, 0, NV84_EVO_CRTC(nv_crtc->index, CURSOR_DMA), 1); 59 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, CURSOR_CTRL), 2); 64 BEGIN_RING(evo, 0, NV50_EVO_UPDATE, 1); 89 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, CURSOR_CTRL), 2); 93 BEGIN_RING(evo, 0, NV84_EVO_CRTC(nv_crtc->index, CURSOR_DMA), 1); 98 BEGIN_RING(evo, 0, NV50_EVO_UPDATE, 1);
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H A D | nv50_crtc.c | 82 BEGIN_RING(evo, 0, NV50_EVO_CRTC(index, CLUT_MODE), 2); 86 BEGIN_RING(evo, 0, NV84_EVO_CRTC(index, CLUT_DMA), 1); 90 BEGIN_RING(evo, 0, NV50_EVO_CRTC(index, FB_DMA), 1); 103 BEGIN_RING(evo, 0, NV50_EVO_CRTC(index, CLUT_MODE), 2); 110 BEGIN_RING(evo, 0, NV84_EVO_CRTC(index, CLUT_DMA), 1); 114 BEGIN_RING(evo, 0, NV50_EVO_CRTC(index, FB_OFFSET), 2); 117 BEGIN_RING(evo, 0, NV50_EVO_CRTC(index, FB_DMA), 1); 150 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, DITHER_CTRL), 1); 157 BEGIN_RING(evo, 0, NV50_EVO_UPDATE, 1); 242 BEGIN_RING(ev [all...] |
H A D | nv50_dac.c | 59 BEGIN_RING(evo, 0, NV50_EVO_DAC(nv_encoder->or, MODE_CTRL), 1); 61 BEGIN_RING(evo, 0, NV50_EVO_UPDATE, 1); 253 BEGIN_RING(evo, 0, NV50_EVO_DAC(nv_encoder->or, MODE_CTRL), 2);
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H A D | nouveau_dma.c | 111 BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_NAME, 1); 113 BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_DMA_NOTIFY, 1); 120 BEGIN_RING(chan, NvSubSw, 0, 1);
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H A D | nv50_sor.c | 59 BEGIN_RING(evo, 0, NV50_EVO_SOR(nv_encoder->or, MODE_CTRL), 1); 61 BEGIN_RING(evo, 0, NV50_EVO_UPDATE, 1); 237 BEGIN_RING(evo, 0, NV50_EVO_SOR(nv_encoder->or, MODE_CTRL), 1);
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H A D | nouveau_dma.h | 127 BEGIN_RING(struct nouveau_channel *chan, int subc, int mthd, int size) function
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/gpu/drm/radeon/ |
H A D | r300_cmdbuf.c | 73 BEGIN_RING(6 + nr * 2); 140 BEGIN_RING(2); 146 BEGIN_RING(2); 150 BEGIN_RING(2); 334 BEGIN_RING(1 + sz); 378 BEGIN_RING(1 + sz); 409 BEGIN_RING(6); 420 BEGIN_RING(3 + sz * 4); 426 BEGIN_RING(2); 446 BEGIN_RING(1 [all...] |
H A D | radeon_state.c | 184 BEGIN_RING(2); 456 BEGIN_RING(4); 488 BEGIN_RING(14); 507 BEGIN_RING(2); 514 BEGIN_RING(5); 524 BEGIN_RING(5); 534 BEGIN_RING(4); 543 BEGIN_RING(7); 555 BEGIN_RING(4); 564 BEGIN_RING( [all...] |
H A D | r600_blit.c | 62 BEGIN_RING(21 + 2); 69 BEGIN_RING(21); 115 BEGIN_RING(5); 151 BEGIN_RING(9 + 12); 196 BEGIN_RING(9); 244 BEGIN_RING(9); 264 BEGIN_RING(12); 288 BEGIN_RING(10); 463 BEGIN_RING(r7xx_default_size + 10); 467 BEGIN_RING(r6xx_default_siz [all...] |
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/gpu/drm/radeon/ |
H A D | r300_cmdbuf.c | 73 BEGIN_RING(6 + nr * 2); 140 BEGIN_RING(2); 146 BEGIN_RING(2); 150 BEGIN_RING(2); 334 BEGIN_RING(1 + sz); 378 BEGIN_RING(1 + sz); 409 BEGIN_RING(6); 420 BEGIN_RING(3 + sz * 4); 426 BEGIN_RING(2); 446 BEGIN_RING(1 [all...] |
H A D | radeon_state.c | 184 BEGIN_RING(2); 456 BEGIN_RING(4); 488 BEGIN_RING(14); 507 BEGIN_RING(2); 514 BEGIN_RING(5); 524 BEGIN_RING(5); 534 BEGIN_RING(4); 543 BEGIN_RING(7); 555 BEGIN_RING(4); 564 BEGIN_RING( [all...] |
H A D | r600_blit.c | 62 BEGIN_RING(21 + 2); 69 BEGIN_RING(21); 115 BEGIN_RING(5); 151 BEGIN_RING(9 + 12); 196 BEGIN_RING(9); 244 BEGIN_RING(9); 264 BEGIN_RING(12); 288 BEGIN_RING(10); 463 BEGIN_RING(r7xx_default_size + 10); 467 BEGIN_RING(r6xx_default_siz [all...] |
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/gpu/drm/r128/ |
H A D | r128_state.c | 47 BEGIN_RING((count < 3 ? count : 3) * 5 + 2); 90 BEGIN_RING(2); 105 BEGIN_RING(13); 131 BEGIN_RING(3); 147 BEGIN_RING(5); 166 BEGIN_RING(2); 183 BEGIN_RING(7 + R128_MAX_TEXTURE_LEVELS); 208 BEGIN_RING(5 + R128_MAX_TEXTURE_LEVELS); 303 BEGIN_RING(6); 385 BEGIN_RING( [all...] |
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/gpu/drm/r128/ |
H A D | r128_state.c | 47 BEGIN_RING((count < 3 ? count : 3) * 5 + 2); 90 BEGIN_RING(2); 105 BEGIN_RING(13); 131 BEGIN_RING(3); 147 BEGIN_RING(5); 166 BEGIN_RING(2); 183 BEGIN_RING(7 + R128_MAX_TEXTURE_LEVELS); 208 BEGIN_RING(5 + R128_MAX_TEXTURE_LEVELS); 303 BEGIN_RING(6); 385 BEGIN_RING( [all...] |