Searched refs:AT91_BASE_SYS (Results 1 - 25 of 122) sorted by relevance

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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mach-at91/include/mach/
H A Dat91x40.h33 * System Peripherals (offset from AT91_BASE_SYS)
35 #define AT91_BASE_SYS 0xffc00000 macro
37 #define AT91_EBI (0xffe00000 - AT91_BASE_SYS) /* External Bus Interface */
38 #define AT91_SF (0xfff00000 - AT91_BASE_SYS) /* Special Function */
39 #define AT91_USART1 (0xfffcc000 - AT91_BASE_SYS) /* USART 1 */
40 #define AT91_USART0 (0xfffd0000 - AT91_BASE_SYS) /* USART 0 */
41 #define AT91_TC (0xfffe0000 - AT91_BASE_SYS) /* Timer Counter */
42 #define AT91_PIOA (0xffff0000 - AT91_BASE_SYS) /* PIO Controller A */
43 #define AT91_PS (0xffff4000 - AT91_BASE_SYS) /* Power Save */
44 #define AT91_WD (0xffff8000 - AT91_BASE_SYS) /* Watchdo
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H A Dat91cap9.h80 #define AT91_BASE_SYS 0xffffe200 macro
83 * System Peripherals (offset from AT91_BASE_SYS)
85 #define AT91_ECC (0xffffe200 - AT91_BASE_SYS)
86 #define AT91_BCRAMC (0xffffe400 - AT91_BASE_SYS)
87 #define AT91_DDRSDRC0 (0xffffe600 - AT91_BASE_SYS)
88 #define AT91_SMC (0xffffe800 - AT91_BASE_SYS)
89 #define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS)
90 #define AT91_CCFG (0xffffeb10 - AT91_BASE_SYS)
91 #define AT91_DMA (0xffffec00 - AT91_BASE_SYS)
92 #define AT91_DBGU (0xffffee00 - AT91_BASE_SYS)
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H A Dat91sam9rl.h69 #define AT91_BASE_SYS 0xffffc000 macro
73 * System Peripherals (offset from AT91_BASE_SYS)
75 #define AT91_DMA (0xffffe600 - AT91_BASE_SYS)
76 #define AT91_ECC (0xffffe800 - AT91_BASE_SYS)
77 #define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS)
78 #define AT91_SMC (0xffffec00 - AT91_BASE_SYS)
79 #define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
80 #define AT91_CCFG (0xffffef10 - AT91_BASE_SYS)
81 #define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
82 #define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
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H A Dat91sam9261.h65 #define AT91_BASE_SYS 0xffffea00 macro
69 * System Peripherals (offset from AT91_BASE_SYS)
71 #define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS)
72 #define AT91_SMC (0xffffec00 - AT91_BASE_SYS)
73 #define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
74 #define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
75 #define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
76 #define AT91_PIOA (0xfffff400 - AT91_BASE_SYS)
77 #define AT91_PIOB (0xfffff600 - AT91_BASE_SYS)
78 #define AT91_PIOC (0xfffff800 - AT91_BASE_SYS)
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H A Dat91sam9263.h75 #define AT91_BASE_SYS 0xffffe000 macro
78 * System Peripherals (offset from AT91_BASE_SYS)
80 #define AT91_ECC0 (0xffffe000 - AT91_BASE_SYS)
81 #define AT91_SDRAMC0 (0xffffe200 - AT91_BASE_SYS)
82 #define AT91_SMC0 (0xffffe400 - AT91_BASE_SYS)
83 #define AT91_ECC1 (0xffffe600 - AT91_BASE_SYS)
84 #define AT91_SDRAMC1 (0xffffe800 - AT91_BASE_SYS)
85 #define AT91_SMC1 (0xffffea00 - AT91_BASE_SYS)
86 #define AT91_MATRIX (0xffffec00 - AT91_BASE_SYS)
87 #define AT91_CCFG (0xffffed10 - AT91_BASE_SYS)
[all...]
H A Dat91sam9g45.h87 #define AT91_BASE_SYS 0xffffe200 macro
90 * System Peripherals (offset from AT91_BASE_SYS)
92 #define AT91_ECC (0xffffe200 - AT91_BASE_SYS)
93 #define AT91_DDRSDRC1 (0xffffe400 - AT91_BASE_SYS)
94 #define AT91_DDRSDRC0 (0xffffe600 - AT91_BASE_SYS)
95 #define AT91_SMC (0xffffe800 - AT91_BASE_SYS)
96 #define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS)
97 #define AT91_DMA (0xffffec00 - AT91_BASE_SYS)
98 #define AT91_DBGU (0xffffee00 - AT91_BASE_SYS)
99 #define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
[all...]
H A Dat91rm9200.h79 #define AT91_BASE_SYS 0xfffff000 macro
83 * System Peripherals (offset from AT91_BASE_SYS)
85 #define AT91_AIC (0xfffff000 - AT91_BASE_SYS) /* Advanced Interrupt Controller */
86 #define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) /* Debug Unit */
87 #define AT91_PIOA (0xfffff400 - AT91_BASE_SYS) /* PIO Controller A */
88 #define AT91_PIOB (0xfffff600 - AT91_BASE_SYS) /* PIO Controller B */
89 #define AT91_PIOC (0xfffff800 - AT91_BASE_SYS) /* PIO Controller C */
90 #define AT91_PIOD (0xfffffa00 - AT91_BASE_SYS) /* PIO Controller D */
91 #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) /* Power Management Controller */
92 #define AT91_ST (0xfffffd00 - AT91_BASE_SYS) /* Syste
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H A Dat572d940hf.h86 #define AT91_BASE_SYS 0xffffea00 macro
90 * System Peripherals (offset from AT91_BASE_SYS)
92 #define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS)
93 #define AT91_SMC (0xffffec00 - AT91_BASE_SYS)
94 #define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
95 #define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
96 #define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
97 #define AT91_PIOA (0xfffff400 - AT91_BASE_SYS)
98 #define AT91_PIOB (0xfffff600 - AT91_BASE_SYS)
99 #define AT91_PIOC (0xfffff800 - AT91_BASE_SYS)
[all...]
H A Dat91sam9260.h81 #define AT91_BASE_SYS 0xffffe800 macro
84 * System Peripherals (offset from AT91_BASE_SYS)
86 #define AT91_ECC (0xffffe800 - AT91_BASE_SYS)
87 #define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS)
88 #define AT91_SMC (0xffffec00 - AT91_BASE_SYS)
89 #define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
90 #define AT91_CCFG (0xffffef10 - AT91_BASE_SYS)
91 #define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
92 #define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
93 #define AT91_PIOA (0xfffff400 - AT91_BASE_SYS)
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H A Dhardware.h53 #define AT91_IO_PHYS_BASE AT91_BASE_SYS
65 #define AT91_VA_BASE_SYS AT91_IO_P2V(AT91_BASE_SYS)
H A Duncompress.h28 #define UART_OFFSET (AT91_DBGU + AT91_BASE_SYS)
H A Ddebug-macro.S20 ldreq \rx, =(AT91_BASE_SYS + AT91_DBGU) @ System peripherals (phys address)
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-at91/include/mach/
H A Dat91x40.h33 * System Peripherals (offset from AT91_BASE_SYS)
35 #define AT91_BASE_SYS 0xffc00000 macro
37 #define AT91_EBI (0xffe00000 - AT91_BASE_SYS) /* External Bus Interface */
38 #define AT91_SF (0xfff00000 - AT91_BASE_SYS) /* Special Function */
39 #define AT91_USART1 (0xfffcc000 - AT91_BASE_SYS) /* USART 1 */
40 #define AT91_USART0 (0xfffd0000 - AT91_BASE_SYS) /* USART 0 */
41 #define AT91_TC (0xfffe0000 - AT91_BASE_SYS) /* Timer Counter */
42 #define AT91_PIOA (0xffff0000 - AT91_BASE_SYS) /* PIO Controller A */
43 #define AT91_PS (0xffff4000 - AT91_BASE_SYS) /* Power Save */
44 #define AT91_WD (0xffff8000 - AT91_BASE_SYS) /* Watchdo
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H A Dat91cap9.h80 #define AT91_BASE_SYS 0xffffe200 macro
83 * System Peripherals (offset from AT91_BASE_SYS)
85 #define AT91_ECC (0xffffe200 - AT91_BASE_SYS)
86 #define AT91_BCRAMC (0xffffe400 - AT91_BASE_SYS)
87 #define AT91_DDRSDRC0 (0xffffe600 - AT91_BASE_SYS)
88 #define AT91_SMC (0xffffe800 - AT91_BASE_SYS)
89 #define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS)
90 #define AT91_CCFG (0xffffeb10 - AT91_BASE_SYS)
91 #define AT91_DMA (0xffffec00 - AT91_BASE_SYS)
92 #define AT91_DBGU (0xffffee00 - AT91_BASE_SYS)
[all...]
H A Dat91sam9rl.h69 #define AT91_BASE_SYS 0xffffc000 macro
73 * System Peripherals (offset from AT91_BASE_SYS)
75 #define AT91_DMA (0xffffe600 - AT91_BASE_SYS)
76 #define AT91_ECC (0xffffe800 - AT91_BASE_SYS)
77 #define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS)
78 #define AT91_SMC (0xffffec00 - AT91_BASE_SYS)
79 #define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
80 #define AT91_CCFG (0xffffef10 - AT91_BASE_SYS)
81 #define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
82 #define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
[all...]
H A Dat91sam9261.h65 #define AT91_BASE_SYS 0xffffea00 macro
69 * System Peripherals (offset from AT91_BASE_SYS)
71 #define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS)
72 #define AT91_SMC (0xffffec00 - AT91_BASE_SYS)
73 #define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
74 #define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
75 #define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
76 #define AT91_PIOA (0xfffff400 - AT91_BASE_SYS)
77 #define AT91_PIOB (0xfffff600 - AT91_BASE_SYS)
78 #define AT91_PIOC (0xfffff800 - AT91_BASE_SYS)
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H A Dat91sam9263.h75 #define AT91_BASE_SYS 0xffffe000 macro
78 * System Peripherals (offset from AT91_BASE_SYS)
80 #define AT91_ECC0 (0xffffe000 - AT91_BASE_SYS)
81 #define AT91_SDRAMC0 (0xffffe200 - AT91_BASE_SYS)
82 #define AT91_SMC0 (0xffffe400 - AT91_BASE_SYS)
83 #define AT91_ECC1 (0xffffe600 - AT91_BASE_SYS)
84 #define AT91_SDRAMC1 (0xffffe800 - AT91_BASE_SYS)
85 #define AT91_SMC1 (0xffffea00 - AT91_BASE_SYS)
86 #define AT91_MATRIX (0xffffec00 - AT91_BASE_SYS)
87 #define AT91_CCFG (0xffffed10 - AT91_BASE_SYS)
[all...]
H A Dat91sam9g45.h87 #define AT91_BASE_SYS 0xffffe200 macro
90 * System Peripherals (offset from AT91_BASE_SYS)
92 #define AT91_ECC (0xffffe200 - AT91_BASE_SYS)
93 #define AT91_DDRSDRC1 (0xffffe400 - AT91_BASE_SYS)
94 #define AT91_DDRSDRC0 (0xffffe600 - AT91_BASE_SYS)
95 #define AT91_SMC (0xffffe800 - AT91_BASE_SYS)
96 #define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS)
97 #define AT91_DMA (0xffffec00 - AT91_BASE_SYS)
98 #define AT91_DBGU (0xffffee00 - AT91_BASE_SYS)
99 #define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
[all...]
H A Dat91rm9200.h79 #define AT91_BASE_SYS 0xfffff000 macro
83 * System Peripherals (offset from AT91_BASE_SYS)
85 #define AT91_AIC (0xfffff000 - AT91_BASE_SYS) /* Advanced Interrupt Controller */
86 #define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) /* Debug Unit */
87 #define AT91_PIOA (0xfffff400 - AT91_BASE_SYS) /* PIO Controller A */
88 #define AT91_PIOB (0xfffff600 - AT91_BASE_SYS) /* PIO Controller B */
89 #define AT91_PIOC (0xfffff800 - AT91_BASE_SYS) /* PIO Controller C */
90 #define AT91_PIOD (0xfffffa00 - AT91_BASE_SYS) /* PIO Controller D */
91 #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) /* Power Management Controller */
92 #define AT91_ST (0xfffffd00 - AT91_BASE_SYS) /* Syste
[all...]
H A Dat572d940hf.h86 #define AT91_BASE_SYS 0xffffea00 macro
90 * System Peripherals (offset from AT91_BASE_SYS)
92 #define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS)
93 #define AT91_SMC (0xffffec00 - AT91_BASE_SYS)
94 #define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
95 #define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
96 #define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
97 #define AT91_PIOA (0xfffff400 - AT91_BASE_SYS)
98 #define AT91_PIOB (0xfffff600 - AT91_BASE_SYS)
99 #define AT91_PIOC (0xfffff800 - AT91_BASE_SYS)
[all...]
H A Dat91sam9260.h81 #define AT91_BASE_SYS 0xffffe800 macro
84 * System Peripherals (offset from AT91_BASE_SYS)
86 #define AT91_ECC (0xffffe800 - AT91_BASE_SYS)
87 #define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS)
88 #define AT91_SMC (0xffffec00 - AT91_BASE_SYS)
89 #define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
90 #define AT91_CCFG (0xffffef10 - AT91_BASE_SYS)
91 #define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
92 #define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
93 #define AT91_PIOA (0xfffff400 - AT91_BASE_SYS)
[all...]
H A Dhardware.h53 #define AT91_IO_PHYS_BASE AT91_BASE_SYS
65 #define AT91_VA_BASE_SYS AT91_IO_P2V(AT91_BASE_SYS)
H A Duncompress.h28 #define UART_OFFSET (AT91_DBGU + AT91_BASE_SYS)
H A Ddebug-macro.S20 ldreq \rx, =(AT91_BASE_SYS + AT91_DBGU) @ System peripherals (phys address)
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mach-at91/
H A Dboard-1arm.c95 .phys_io = AT91_BASE_SYS,

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