Searched refs:ARM_CKCTL (Results 1 - 10 of 10) sorted by relevance
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mach-omap1/ |
H A D | sram.S | 28 mov r3, #OMAP1_IO_ADDRESS(ARM_CKCTL) & 0xff000000 29 orr r3, r3, #OMAP1_IO_ADDRESS(ARM_CKCTL) & 0x00ff0000 30 orr r3, r3, #OMAP1_IO_ADDRESS(ARM_CKCTL) & 0x0000ff00
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H A D | pm.c | 222 #define EN_DSPCK 13 /* ARM_CKCTL */ 284 ARM_SAVE(ARM_CKCTL); 307 omap_writew(omap_readw(ARM_CKCTL) & ~(1 << EN_DSPCK), ARM_CKCTL); 375 ARM_RESTORE(ARM_CKCTL); 444 ARM_SAVE(ARM_CKCTL); 502 ARM_SHOW(ARM_CKCTL),
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H A D | clock_data.c | 193 * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1 203 .enable_reg = OMAP1_IO_ADDRESS(ARM_CKCTL), 787 pr_info("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: " 789 omap_readw(ARM_CKCTL)); 827 omap_writew(cpu_is_omap7xx() ? 0x3005 : 0x1005, ARM_CKCTL); 854 omap_writew(omap_readw(ARM_CKCTL) & 0x2fff, ARM_CKCTL); 856 omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL); local
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H A D | clock.c | 166 int dsor = 1 << (3 & (omap_readw(ARM_CKCTL) >> clk->rate_offset)); 271 regval = omap_readw(ARM_CKCTL); 275 omap_writew(regval, ARM_CKCTL);
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-omap1/ |
H A D | sram.S | 28 mov r3, #OMAP1_IO_ADDRESS(ARM_CKCTL) & 0xff000000 29 orr r3, r3, #OMAP1_IO_ADDRESS(ARM_CKCTL) & 0x00ff0000 30 orr r3, r3, #OMAP1_IO_ADDRESS(ARM_CKCTL) & 0x0000ff00
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H A D | pm.c | 222 #define EN_DSPCK 13 /* ARM_CKCTL */ 284 ARM_SAVE(ARM_CKCTL); 307 omap_writew(omap_readw(ARM_CKCTL) & ~(1 << EN_DSPCK), ARM_CKCTL); 375 ARM_RESTORE(ARM_CKCTL); 444 ARM_SAVE(ARM_CKCTL); 502 ARM_SHOW(ARM_CKCTL),
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H A D | clock_data.c | 193 * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1 203 .enable_reg = OMAP1_IO_ADDRESS(ARM_CKCTL), 787 pr_info("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: " 789 omap_readw(ARM_CKCTL)); 827 omap_writew(cpu_is_omap7xx() ? 0x3005 : 0x1005, ARM_CKCTL); 854 omap_writew(omap_readw(ARM_CKCTL) & 0x2fff, ARM_CKCTL); 856 omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL); local
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H A D | clock.c | 166 int dsor = 1 << (3 & (omap_readw(ARM_CKCTL) >> clk->rate_offset)); 271 regval = omap_readw(ARM_CKCTL); 275 omap_writew(regval, ARM_CKCTL);
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/plat-omap/include/plat/ |
H A D | hardware.h | 73 #define ARM_CKCTL (CLKGEN_REG_BASE + 0x0) macro
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/plat-omap/include/plat/ |
H A D | hardware.h | 73 #define ARM_CKCTL (CLKGEN_REG_BASE + 0x0) macro
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